Starting with FPGAs

[JuniorJack]

What are your CPU temperatures under full load? The 3930k runs very hot and you won't get good results with cheap heatsinks and fans.
(By cheap, I mean really cheap. $30 for a heatsink and $30 for a fan are good enough.)

To be honest i haven't checked temperatures during the long run to generate that project, but i will try to monitor the next time. I have some huge and heavy heatsink with two fans (can't remember the name), it is not the stock cooler that comes with the CPU. But will double check this next time.

[NiHaoMike]

Also check your case temps and BIOS settings. The highest recommended operating temperature for a 3930k is 67C. Mine runs in the low 60s at full load during the summer.

You can't use a stock cooler on a 3930k because there isn't one. (There is a reference design cooler, but that's not exactly a "stock cooler".) Also try using i7z to get detailed stats.

[mrflibble]

Wait, you mean just select bigger device in the project settings, not physically using it ? Then simulate all in the ISE, so
when everything is completed to satisfactory level, select correct device and generate final bitstream that will be loaded
in config memory ?

Precisely. If your design just barely fits in the fpga then the Place & Route has to expend some serious effort to squeeze it all in. If you give it a nice bit of room to work with suddenly things are a lot faster. This approach is not the end-all solution for all cases, but sometimes it can save you a nice bit of time. Especially when you're just trying to figure out how everything works...

[mrflibble]

And on the topic of overclocking & cpu temps ... for fpga work that takes to long I overclock my i5-2500k to 4.7 GHz with a non-stock cooler and it gets to about 60-65 degrees C. This one overclocks to just about 4.9 GHz but I like a bit of margin for stability.

[mikeselectricstuff]

Hi,

As i said, i am complete newbie to FPGA design, so not everything suggested about using simulation makes sense to me yet. But my PC is kinda ok-ish, was top of the range last year - i7 3930k 3,20 Ghz, asus rampage extreme 4 mobo, 32 Gb of quad channel RAM, HD is Samsung SSD 830. My video card is not something worth mentioning, but i have few 5970's laying around, i can put them in, if this would help somehow. The project is on the local, SSD drive, not using network storage.

A simple example like this:

Code: [Select]

entity ucecho is
   port(
      pc      : in unsigned(7 downto 0);
      pb      : out std_logic_vector(7 downto 0);
      CS      : in std_logic;
      CLK     : in std_logic
   );
end ucecho;

architecture RTL of ucecho is

-- signal declaration
signal pb_buf : unsigned(7 downto 0);

begin
    pb <= std_logic_vector( pb_buf ) when CS = '1' else (others => 'Z');

    dpUCECHO: process(CLK)
    begin
         if CLK' event and CLK = '1' then
    if ( pc >= 97 ) and ( pc <= 122)
    then
pb_buf <= pc - 32;
    else
pb_buf <= pc;
    end if;
end if;
    end process dpUCECHO;
   
end RTL;

will take something like 20-30 minutes. The example i was talking about (the one that took the whole morning) is here:

https://github.com/fpgaminer/sha1_collider

It has two instances of SHA-1 (unrolled) and some jtag debug and display control (as far as i can read the code).
It is not my code, i was just curious to play with it, and learn, no pressure or deadlines.

Regards

That simple example should take well under a minute - something is clearly very wrong.
First suggestion would be to remove ALL timing constraints and see what happens.

[marshallh]

Synthesis and fitting for one fully unrolled sha256 core (target is Arria IIGX) takes about 2 hours on my machine. Phenom II X4 @3.9ghz, 16gb ram.

I use a disk filter driver called SuperCache that turns 8gb of my main RAM into a hard drive cache. After the first copmile all the files are living in RAM so after that my HDD is almost never even touched (it does delayed write flush too, fine if you have a UPS

[mrflibble]

That simple example should take well under a minute - something is clearly very wrong.
First suggestion would be to remove ALL timing constraints and see what happens.

See this post later in the thread.

"Update: I am sorry, my previous post was bit misleading, the clear example full generation takes 2 minutes (the 20-30 minutes was with an extra added file, my bad)."

[JuniorJack]

Precisely. If your design just barely fits in the fpga then the Place & Route has to expend some serious effort to squeeze it all in. If you give it a nice bit of room to work with suddenly things are a lot faster. This approach is not the end-all solution for all cases, but sometimes it can save you a nice bit of time. Especially when you're just trying to figure out how everything works...

Thank you! That makes sense. Specially at this stage, where the only thing that makes sense to me is the RTL schematics,
the Verilog syntax is still Chinese to me.