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Are my FETs failing from SOA or dv/dt?

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hlab:
Hello Everyone,

I'm new to the forum but not new to EE.  ;)


About the circuit
First, a little context. I've designed half bridge for high power brushed DC motors (15V at ~40A). During stall, inrush current can go up into the 150 amp range however. Both fets are extremely low RDSon, ~0.8mohm, and never get warm. I've tested it for several weeks now without issues until yesterday when the low side FET decided to become a 3-way pin short. No biggie, probably just bad soldering I thought. Then I tried again with a completely new driver board, and it failed instantly in the same way, all 3 pins of the low side fet shorted together (high side fet is still fine).

Due to several non-ideal design constraints, I had to design this driver in a fairly unconventional way. The motor itself is inaccessible and there is no space for a flyback diode to suppress inductive kickback. Normally this wouldn't be an issue, since the diode in the high side fet should route it back to the motor. However, the return loop through the high side FET has too much impedance to be of any help.


How it works
The way I solved this issue was to soft switch the motor in a controlled way to keep the spike under the VDS limit. As soon as the M2 begins to switch off, the resulting inductive spike travels through the body diode of M1. It then goes through D3 and D2 to try to keep M2 on. In this manner, VDS across M2 is clamped to ~30-35V. It takes ~2uS to fully switch off. I also have an RC snubber circuit across M2 to soak up any high frequency ringing that is present. Yes, I have measured VDS across M2 with my 200MHz scope and it never goes above 36V. I only have cheap probes though, so even if there was a high voltage spike I probably wouldn't see it anyway.


Theories of why it's failing
I'm a little baffled why it took so long to fail the first time if there's something really wrong with my design. But here's a few guesses as to what could be happening.

1. Due to the slow switching, the mosfet die heats up too quickly and destroys the depletion region (probably the most likely imo)
2. Brush noise from the motor causes the VDS rating to be exceeded and fet is destroyed by avalanche current
3. Large dv/dt is causing VGS to be exceeded (I think this is less likely due to RC snubber present)
4. Other high voltage transients are exceeding the maximum VGS rating (20V)


Any ideas for troubleshooting or things I may have missed?

hlab:
Upon further inspection, it seems that 2uS switching time is well within the datasheet SOA.

Also, In LTSpice the slope of the inductive spike is less than 0.2V/ns, which should be ok right?

ANTALIFE:
As a first step I would capture some gate & drain waveforms for both MOSFETs and share them on here

hlab:
Well it seems that my previous scope readings were incorrect. I swapped out both fets rated for 60V, and now I'm getting 100V spikes on the drain. Is there any reason the zener diode wouldn't be clamping the spikes as intended?

Attached screenshot is VDS x10 during turnoff.

ANTALIFE:

--- Quote from: hlab on January 21, 2022, 03:43:40 am ---Well it seems that my previous scope readings were incorrect. I swapped out both fets rated for 60V, and now I'm getting 100V spikes on the drain. Is there any reason the zener diode wouldn't be clamping the spikes as intended?

Attached screenshot is VDS x10 during turnoff.

--- End quote ---

Show us where your zener is placed

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