Are there SPI multiplexer ICs?

[zapta]

>> Use the biggest FPGA you can afford so that you don't run out of resources.

Thanks a great idea. Can you recommend me one?

[Siwastaja]

>> Use the biggest FPGA you can afford so that you don't run out of resources.

Thanks a great idea. Can you recommend me one?

I worked with FPGAs over 10 years ago but did not find much use for them in projects I now choose to do. Altera Stratix II was a cool thing, and I played with some of the largest models with catalogue price of $10000 or so, per chip. Altera is now Intel and a lot has changed, probably, but one thing remains: the higher the cost, the bigger and better it is.

[zapta]

Currently this programmable device is at the top of my list. Trying to fit a minimalist design. It's small, inexpensive, stand alone, and can even be program in circuit via I2C.

https://www.mouser.com/ProductDetail/Renesas-Dialog/SLG46826G?qs=%252B6g0mu59x7Lz4SMy5idICg%3D%3D

[zapta]

I was able to map a proof of concept design to a $1.5 SLG46826G SPLID.  With this design, the address IC sits near each SPI device on the bus, providing it an stripped down CS/SCLK/MOSI, after detecting the correct address in the first byte. This design supports for different addresses but more can be added. Also, polarity control for the clk and data can be added.

The SLG46826G can be programmed in circuit via the I2C port or one time before assembling it.

Am I missing something?

[dietert1]

In order to send the device selection as the first byte in a SPI transaction, this would require a shift register that drives a decoder. The decoder outputs select one of the devices after receiving the first byte. This needs one output port as CS for the shift register (shift enable, decoder output disable) and likely another output port to delimit the SPI transaction. I don't think one needs to manipulate the three SPI bus signals, as SPI devices include logic to remain inactive without CS.
If there are less than eight devices, one can use just a shifter with sparse code. Maybe a 74hc164 serves the purpose.

Regards, Dieter

[zapta]

>> I don't think one needs to manipulate the three SPI bus signals, as SPI devices include logic to remain inactive without CS.

That's correct. I added it because there was free pins and logic but it's optional.

It's also provides buffering which allows to build trees of addressable SPI devices, similar to the diagram below.

[Nominal Animal]

I am a hobbyist with no FPGA experience at all, but I would look at Lattice ICE40LP384-SG32, which Mouser sells for 2€ in singles, and has plenty in stock; I believe but am not certain that it is supported by the open source IceStorm tools too.

I would use five pins between the microcontroller and the FPGA: SCLK, MISO, MOSI, /CS (optional), and a separate pin to reset the FPGA multiplexer if a SPI transfer is interrupted.

Each transfer would begin with a 32-bit routing word.  The first 8 bits would control eight separate /CS pins, optionally connected to a TI TXU0304 voltage level shifter enable pins (allowing one to electrically disconnect a SPI sub-bus).  The next two bits would control the SPI mode, next four bits the word size (4-16), and the last 18 bits the transfer size in words.  (Maximum single transfer would then be 262,144 words.  Alternatively, use the 22 last bits for the transfer size in bits.)

The following bits would be copied over the FPGA, then all /CS pins disabled and input word size reset (to 8 or 16 bits, doesn't matter); and if possible, the bus-side SCLK, MISO, and MOSI tri-stated.  For synchronization purposes, a routing word with all zeros should be a no-operation.

On the bus side, there would be 11 pins: SCLK, MISO, MOSI, and eight /CS pins.  Passing the clock and data signals through the FPGA ensures the /CS pin stays in sync.  Internally, the FPGA can implement an up to 32 SPI clock cycle FIFO (meaning the output is 32 bits later than the input), synchronized to the input SCLK, as long as either the microcontroller appends 32 extra SPI clock cycles after the last transfer, or the FPGA can synthesize the extra 32 clock cycles at the same frequency as the input SCLK.  (The zero routing word is not needed in the middle of a DMA transfer, only at the end.)
So, it really should not be a complicated state machine at all.

I did wonder whether one could use one of the cheap (<$1) ARM Cortex-M0/M0+ MCUs for this instead.  Both HK32F030M and CW32F003 have only one SPI, but STM32G030F6 (0.44€ in singles at LCSC, 1€ at Mouser) has two.  The trick with this approach is that the bus SPI SCLK frequency must be equal or higher than the SCLK frequency from the main microcontroller; perhaps by tying its clock to the main microcontrollers oscillator, or gating the main microcontroller SCLK as the bus SCLK somehow.  Otherwise, the data starts piling up in the bus multiplexer.  Unlike I²C, SPI has no clock stretching to throttle the data.

[zapta]

The  ICE40LP384-SG32 looks as a good choice and it may be supported by open source toolchain (?)  https://f4pga.org/.

In a 3.3v system, does it require an external LDO for the Vcc or other voltage rails?  Any other external components other than decoupling capacitors?

[Nominal Animal]

Again, I'm a total newbie with FPGAs, and know nothing but theory/theoretical stuff, so hopefully others will pipe up about this.

In a 3.3v system, does it require an external LDO for the Vcc or other voltage rails?

3.3V for the I/O (LVCMOS33), and 1.2V for the core (about 8mA at startup) and for Vpp_2v5 (about 4mA).  They do need to be provided in the correct sequence at start-up.

Any other external components other than decoupling capacitors?

See iCE40 Hardware Checklist.  You'll probably want some external pull-up resistors and a SPI SS pull-down resistor.

You do need to provide a reference clock to iCE40LP320-SG32, so you do need to provide an oscillator for SYSCLK pin; probably connecting it to GBIN6 pin.  The Olimex iCE40HX1K-EVB uses a 100 MHz one, and LP384 and HX1K are in the same family (some details differ, but they're described in the same datasheet), so perhaps take a look at the KiCAD files for ideas?

[SiliconWizard]

You can have a look at this project (and you could buy one board while you're designing your own, it's pretty cheap, and this way you'll have something working to start with): https://github.com/wuxx/icesugar-nano
It's a very barebones board around a iCE40LP with no excess fat, so easy to figure out.

[zapta]

Is this FPGA more standalone than the ICE40?  That is, just bypass capacitors on the 3.3V rail?

EDIT: Adding the missing link https://www.digikey.com/en/products/detail/lattice-semiconductor-corporation/LCMXO2-256HC-4SG32C/3232671

[Nominal Animal]

The icesugar-nano uses a PWM pin from the microcontroller as the clock input.

So, with iCE40LP's and iCE40HX's you need 3.3V and 1.2V, a bunch of bypass capacitors, and a couple of resistors.

[zapta]

Is this one standalone?  That is only 3.3V with bypass capacitors and everything else, including LDOs and clock sources are internal.

https://www.digikey.com/en/products/detail/lattice-semiconductor-corporation/LCMXO2-256HC-4SG32C/3232671

[dietert1]

Yes, there are two versions: ZE with 1.2 V core supply and HC with no special core voltage. Anyway for a 256 device the difference in static power consumption will be about 1 mA - in case it matters. I remember using a MachXO2 evaluation board some years ago and found it pretty straightforward to get results.

Regards, Dieter

[zapta]

I ended up designing the SPI address selector using Renesas SLG46826G SPLD. It passes the simulation and I am waiting for the parts to arrive to test it in a real circuit.

It uses the 4 LSB bits of the first byte to select 1 of 16 SPI devices and in case of an address match, passes the CS, CLK, and MOSI, to the device. The addressing can be cascaded such that the number of devices is unlimited as long as propagation delays are observed.

The gating of CLK and MOSI is optional and was done mainly as buffering, to reduce the per-device load on those signals.

SCLK and SDA are used to program the device using I2C and A0, A1, A2, A3 inputs should be hard wired to a unique device address.









https://github.com/zapta/GreenPAKs/tree/main/addressable_spi