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ASK/OOK implementation with discreet logic
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smoothVTer:
In a current project I am working on, I am stuck with using a family of uC's that do not have built-in IR modulation logic.  I know I can use timers & compare registers to do ASK/OOK modulation, albeit the solution is messy to make the carrier & envelope signals work together in the uC & firmware.    So I thought of a possible solution that may make the modulation easier using external discreet external logic, but precisely what logic to use in what combination confuses me. 

Thus I am asking for help from all you digitally-minded folk out there in EEV-Land!

Assuming that: 
(a)  There is always present a 36kHz carrier signal on a uC pin;
(b)  The envelope signal would have a minimum HIGH or LOW time of  >= 1 ms;
(c)   If the envelope signal goes high in the middle of a carrier pulse HIGH time,  the output is latched low until the next rising edge of the carrier, at which point the output goes high


(d)   If the envelope signal goes low in the middle of a carrier pulse HIGH time, the output is latched high until the next falling edge of the carrier, at which point the output goes low

To illustrate this behavior with a diagram:



Area labeled #1:   Output waits until the next rising edge of the carrier before it is asserted
Area labeled #2:   Output waits until the next falling edge of the carrier before it is de-asserted
Area labeled #3 & #4:  Normal gating operation of envelope on carrier

Given that the carrier and envelope already exist on the uC pins,  how would the output waveform be constructed using the minimum number of flip-flops & logic gates?
SiliconWizard:
Sure. This is a typical thing. You only need a flip-flop and an AND gate. Like so:



For the flip-flop, you can use a 74LVC1G74 for instance, and a 74LVC1G08 for the AND gate.
smoothVTer:
Thank you!

Simulation works out;  I forgot LTSpice allows logic sims like this.  Neat.

Just for clarification:  The DFF is required to be rising-edge triggered in this implementation, correct?
SiliconWizard:

--- Quote from: smoothVTer on September 13, 2019, 09:16:09 pm ---Thank you!

Simulation works out;  I forgot LTSpice allows logic sims like this.  Neat.

Just for clarification:  The DFF is required to be rising-edge triggered in this implementation, correct?

--- End quote ---

Yes and yes. For LTSpice, yes it has basic logic gates in the Digital category. Just one thing to know is that they have a default logic high level of 1V. You can change this in the component attributes dialog (but for just logic simulation, you don't care about that...)

Due to the propagation delay of the flip-flop (however small), this circuit should be actually glitch-less. I'll leave it as an exercise to figure out the corner cases.
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