Electronics > Projects, Designs, and Technical Stuff
Audio DACs and some odd frequency goings on.
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hamster_nz:
Oh, I've just seen in the data sheet, that the specs are quoted at

"Full-Scale Output Sine Wave, 997 Hz"

Humm, might try at that frequency, and see if it is then within spec...  maybe it is once again a case of dodgy DAC specifications.
fcb:
Could these be idle-tones? Level does seem quite high for idle tones?  How clean is your PSU?
BrianHG:

--- Quote from: hamster_nz on December 02, 2019, 12:15:54 am ---
--- Quote from: jbb on December 01, 2019, 11:38:42 pm ---Are you outputting an ADC or DAC clock from the FPGA? If so, I hear it can be helpful to use a two clock system (same frequency, with 0 degree clock and 180 degree clock) for the output drivers, a DDR output driver, and a fixed output of “10” to provide a very even 50% duty cycle clock with low jitter.

--- End quote ---
Yes, I am using a clock forwarding using a DDR register for those very reasons. On the FPGA I'm using the DDR primitive can work with just one clock.

I'm thinking of knocking up a very simple I2S test case - outputs 0, 7207992, -7207992, which should be a perfect sine at Fs/3, and will be easy to verify with a logic analyzer.

--- End quote ---
DDR outputs are noisy.  Especially when it comes to trying to get that jitter and edge noise down.
Even a compiler PC internal timing simulation reveals the slight inconsistencies of a DDR output.

Example, in my soft serializer simulation, if you look here:
Image #1 shows the hookup.
Image #5 shows the pin-pin timing with a 100ps grid.
Image #7 shows a reconnect to an SDR output with DFF driving the IO.
Image #9 shows a closeup of the IO skew timing with a 100pf grid.
https://www.eevblog.com/forum/fpga/fpga-soft-serializer/msg2804118/#msg2804118

Now, if you want to see the difference of using normal outputs and 'fast output register' outputs,
Image #3 here without 'Fast output Registers', YES that's 1ns per division.
Image #4 is where the output group has the 'Fast Output Register' assignment enabled. (1ns / division )
https://www.eevblog.com/forum/fpga/fpga-soft-serializer/msg2803150/#msg2803150
hamster_nz:

--- Quote from: fcb on December 02, 2019, 01:31:46 am ---Could these be idle-tones? Level does seem quite high for idle tones?  How clean is your PSU?

--- End quote ---

Unsure of what idle-tones are, but the PSU is now quite clean (had some issues early on, but that was due to my stuff-up).

When I bypass the filtering inductor on the path to the DACs Vcc I do get to see some PSU noise. The PSU noise remains pretty consistent when I change the test signal's frequency and amplitude.
SiliconWizard:
Have you tried something very simple: sending all zeroes to the DAC and look at the output?
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