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Audio DACs and some odd frequency goings on.
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jbb:

--- Quote from: hamster_nz on December 03, 2019, 10:17:50 am ---The biggest problem is that my signal generator is a 14-bit DDS - so when connected direct to the input I get the fundamental and then an harmonic at -72db or so. Not really good enough for testing audio.

--- End quote ---

Everyone loves a test equipment surprise!  Or something like that...

Direct Digital Synthesis (DDS) instruments are great because they can give really consistent performance at a good price point (i.e. without a truckload of special analog components).  DDS instruments are terrible because they generate artifacts in non-obvious fashion with stuff like aliasing and spurs, instead of good old fashioned harmonics and drift.

The good news is that you've got an FPGA with logic resources inside.  That means you can build your own high resolution DDS core to provide a well-known all-digital test waveform with lots of bits.   I got very good use out of this magazine article when design a DDS in the past.

Let's see what we can do:

* Set output width M=16 bits
* Expect SNR = −6.02M−1.76dB = -95 dB
* Set phase resolution P = M + 1 = 17 bits
* For sine LUT, only store 1/4 of the full wave; save 2 bits of length.  LUT length = 2^(P-2) = 32768 entries
* For sine LUT, only store sine(phi)-2 phi / pi; save 2 bits of word size. LUT word size = M-2 = 14 bits.
Note: the word size tweak may be pointless given the properties of your FPGA block RAMs...
The LUT will be quite large (further compression methods are available if you feel keen, see the magazine article), but should still fit into many cheap FPGAs.  What FPGA are you using?

Given that the output rate is going to be much less than the FPGA clock rate, you can (with suitable address/data multiplexing) re-use the LUT for multiple DDS generators.  So you could generate multiple independent tones for things like IMD testing.
hamster_nz:

--- Quote from: jbb on December 03, 2019, 07:09:41 pm ---
--- Quote from: hamster_nz on December 03, 2019, 10:17:50 am ---The biggest problem is that my signal generator is a 14-bit DDS - so when connected direct to the input I get the fundamental and then an harmonic at -72db or so. Not really good enough for testing audio.

--- End quote ---

Everyone loves a test equipment surprise!  Or something like that...

Direct Digital Synthesis (DDS) instruments are great because they can give really consistent performance at a good price point (i.e. without a truckload of special analog components).  DDS instruments are terrible because they generate artifacts in non-obvious fashion with stuff like aliasing and spurs, instead of good old fashioned harmonics and drift.

The good news is that you've got an FPGA with logic resources inside.  That means you can build your own high resolution DDS core to provide a well-known all-digital test waveform with lots of bits.   I got very good use out of this magazine article when design a DDS in the past.

Let's see what we can do:

* Set output width M=16 bits
* Expect SNR = −6.02M−1.76dB = -95 dB
* Set phase resolution P = M + 1 = 17 bits
* For sine LUT, only store 1/4 of the full wave; save 2 bits of length.  LUT length = 2^(P-2) = 32768 entries
* For sine LUT, only store sine(phi)-2 phi / pi; save 2 bits of word size. LUT word size = M-2 = 14 bits.
Note: the word size tweak may be pointless given the properties of your FPGA block RAMs...
The LUT will be quite large (further compression methods are available if you feel keen, see the magazine article), but should still fit into many cheap FPGAs.  What FPGA are you using?

Given that the output rate is going to be much less than the FPGA clock rate, you can (with suitable address/data multiplexing) re-use the LUT for multiple DDS generators.  So you could generate multiple independent tones for things like IMD testing.

--- End quote ---

Exactly - which is what I am building this board for, it's a platform for mucking around with DSP. I also have used CORDIC before, so generating next-to-perfect 24-bit samples is a piece of cake... (well, maybe '24 successive better approximations' would be a bit closer to the truth than a 'piece of cake').
hamster_nz:

--- Quote from: macboy on December 03, 2019, 05:36:20 pm ---
--- Quote from: hamster_nz on December 01, 2019, 08:24:03 pm ---...
The DAC being used is a Cirrus Logic CS4344 - https://statics.cirrus.com/pubs/proDatasheet/CS4344-45-48_F2.pdf

MCLK is as smidgen off of 36.864MHz (like 0.01% off), due to not being able to nail it with the valid FPGA's PLL multipler/divider combinations. Maybe I should try clocking directly from the 12MHz oscillator?
...

--- End quote ---
Actual precise frequency of MCLK doesn't matter. But make sure that it is exactly 768x (in your case) the sample rate (LRCLK). They must be synchronous. Close isn't close enough.  You said about 0.01% off... well that's in the single digit kHz territory so it would explain your spurious sidebands if you are using asynchronous clocks. Page 12 of datasheet: "MCLK/LRCK must be an integer ratio".

--- End quote ---

When using the PLL, the MCLK I'm using is 36.86311 MHz (rather than the "on spec" 36.864), and the SCLK and LRCLK generated by dividing that down (2.303 MHz and 47,999.1 S/s, and twice that when running at ~96kS/s), so everything is derived from the same reference clock.

I've also been using just 36.0MHz (to avoid fractional multiply/divide in the FPGA's MMCM) which is 46,875 S/s, to see if that makes a difference.
bson:

--- Quote from: hamster_nz on December 03, 2019, 08:35:33 pm ---When using the PLL,

--- End quote ---
Is that an integer-N synthesizer?  If so, there's another potential source of spurs.
capt bullshot:
Quite an interesting topic.
Having read all the posts, IMO the side frequencies are a result of some non-exactly matching frequencies (MCLK to SCLK/LRCLK ratio or phase noise), maybe even internal to the DAC chip. Looks like this chip has some kind of internal "magic" re-sampling capabilities that might play a tricky game on you. So my only advice would be to avoid any kind of FPGA specific clock generator circuitry, feed the FPGA directly from e.g. a 36MHz oscillator and derive all frequencies by using your own (simple) dividers to ensure exact integer ratios of these frequencies. I wouldn't expect side tones like the ones you shown from even the cheapest audio DAC.
As others said, for the ADC/DAC to operate properly in an isolated setup like yours, it isn't necessary to hit the exact 36.864MHz MCLK, anything within some MHz around will do as long as the other criteria (integer and synchronous ratio MCLK to SCLK) are met.
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