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Audio DACs and some odd frequency goings on.
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SiliconWizard:

--- Quote from: hamster_nz on December 03, 2019, 08:35:33 pm ---When using the PLL, the MCLK I'm using is 36.86311 MHz (rather than the "on spec" 36.864), and the SCLK and LRCLK generated by dividing that down (2.303 MHz and 47,999.1 S/s, and twice that when running at ~96kS/s), so everything is derived from the same reference clock.

--- End quote ---

For generating the bit clock (SCLK?) it's fine IMO, but I don't think it's a good idea for generating LRCLK. I usually generate both the data output bits AND LRCLK from SCLK in a process.
hamster_nz:
A very late update. The next revision of the board was much better - improved grounding (well, half-decent grounding) got rid of a lot of noise, and the output is looking much cleaner.

Next up I want to replace the electros with equivalent MLCCs on one side of one channel and see if it makes a measurable difference...

Pictures are top-to-botom:

- New board

- Old board

- Signal generator direct to input.
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