Oh, I switched my AD2 sampling into 'average' rather than 'decimate' mode, so now the spectrum looks a lot better for the noise floor, with it matching that expected from a audio DAC.
What is AD2?
For the noise floor yes, but otherwise it looks pretty poor compared to even an average 24-bit audio DAC as far as THD is concerned. You definitely have some issue there. Not sure what it is without more info.
What is your MCLK frequency, and are you 100% sure of your I2S transmit block?
AD2 => Digilent Analog Discovery 2, just using it a test bench for this, as both the input and outputs are 14-bit ADC, 100MS/s
The DAC being used is a Cirrus Logic CS4344 -
https://statics.cirrus.com/pubs/proDatasheet/CS4344-45-48_F2.pdfMCLK is as smidgen off of 36.864MHz (like 0.01% off), due to not being able to nail it with the valid FPGA's PLL multipler/divider combinations. Maybe I should try clocking directly from the 12MHz oscillator?
Tonight I will snoop the I2S bus while sending a test tone from a lookup table in the FPGA, and check that the values seen match those in the table.
Do you have both ends set to single channel? Looks like the MSB is flipping, which could possibly be the case if the ADC is sending stereo while the DAC expects mono.
I'd stick my MSO probe on there and check timing, waveform shapes (ringing, overshoot, runts, crosstalk, etc), and that it all looks like it should.
Both ends are set to stereo, and can have test signal down one channel at 1V p-p while the other channel remains quite, so it doesn't look like the are getting messed up on either the digital or analog side of the DAC.
All I2S waveforms look great (well, given the limitations of a 100MHz scope looking at the 36MHz clock) - but the slower LRCK BCLK and SDAT signals are all nice and square. But just in case I've got a Rev2 board in the works that will have series resistors on the digital signals in case it is needed.
I was listening to the whole ADC->FPGA->SRAM->FPGA->DAC chain, at "moderate" volume and it sounds fine to my aged ears. No dogs in the neighbourhood started howling

Oh, I've just realized that I could use my PMOD I2S (
https://reference.digilentinc.com/reference/pmod/pmodi2s/reference-manual) as a comparison to see if it is just my design. It uses the same part, but the forgot the output filtering caps (or more likely left them off because optimal values depends on the sample rate). I'll add that too to the todo list for tonight...