CPU Board #2The un-answered questions on these still bothered me, plus the industrial surplus seller was nice enough to agree to a massive discount, so I got a couple more boards from this same set. One of them was a 2nd copy (different revision) of the CPU board, to decap the chips and sort out what everything was doing.
Ken Shirriff kindly offered to take some die shots after I contacted him about a different project, and so I got to work with a knife and coping saw (he decapped the tricker ones himself like the ceramic DIP packages, and the MIL-STD-1553 transceiver).
Before:
One of the differences, as you can see in that last photo, is that what was an empty socket on the other CPU board has a little ceramic daughterboard here, with two EEPROMs (AT28HC64) and a 54FCT139 (dual 2-bit/1-of-4 decoder) to select between them.
After:
OscillatorIt should be no surprise to anyone that the package marked "12 Mhz" was in fact an oscillator:
You can see the quartz disk here, with electrodes plated on both sides (I accidentally chipped it while opening, it's supposed to be round). There's some other electronics present in the form of a couple ICs and a couple passives. You can build very simple crystal oscillator circuits with only a single transistor, or a logic inverter used as an amplifier, but I'm guessing some of the extra circuitry here might be involved with temperature compensation or ensuring reliable startup.
RAMThe 2x dual-cavity ICs marked with "RM..." custom part numbers turned out to have RAM in both cavities:
I don't know much about different memory topologies at a transistor level, but from looking at the individual memory cells Ken guessed it was SRAM as they seemed too complex to be DRAM. This is consistent with the SRAM that I've seen in other 80's/90's high-reliability computers (such as these Honeywell commercial-aviation boards:
1 and
2), and makes sense because if the extra density of DRAM isn't strictly required, the refresh cycle just adds a whole new set of failure modes and complexity.
The RAM, like a lot of the other ICs onboard, is made by UTMC (United Technologies Microelectronics Center):
CPUThe large quad-flatpack chip I'd assumed was the CPU before turned out to be a standard-cell custom gate array - you can see the very regular layout here, with the irregular interconnections on top:
For digital ICs, this is a popular halfway point in between using only off-the-shelf parts, and going through the massive effort of making a fully-custom IC design. In the standard-cell-ASIC scheme, the manufacturer designs a large array of logic gates, and makes one set of photolithography masks for these. A customer who wants a digital ASIC will then decide how to connect together this fixed set of gates to fit their application, and the manufacturer will make a custom metal-interconnection layer on the chip to fit the custom design (like a hard-wired FPGA). This way, most of the IC fabrication steps and expensive tooling can be the same no matter what, and can be designed once and made in bulk: only the much smaller number of fabrication steps and masks involving the metal layers have to be different for each custom design.
I'm not sure why exactly this uses an ASIC instead of an off-the-shelf processor. There is obviously a lot of I/O interfacing that needs to be done here, to connect the many digital inputs and outputs as well as two separate UARTs for the dual MIL-STD-1553 serial interfaces, so combining that with a simple processor as a single (relatively) miniaturized chip was probably the goal - this still seems like a lot of work though, compared to using off the shelf parts, as even for aerospace-qualified processors and peripherals there was a decent variety available. It's also possible there's some kind of redundancy here, such as two simple processors
operating in lockstep or using voting logic.
I also considered that this might not be a processor after all, but some kind of simple state machine as
rocket engine control doesn't have to be very complex, depending on the engine (for example, the
J-2 engine seems like it's mostly just a series of timers, no feedback loops or complex controls). However, that wouldn't make sense with the EEPROM, which couldn't really be anything but program memory. It's also possible the digital ASIC is just a CPU-bus-to-I/O-and-memory interface, and the CPU itself lives on a different board somewhere, but that wouldn't make a whole lot of sense either: there's no way the CPU would take up an entire board by itself (especially not when as willing as this to use custom parts), and what else would be grouped with it besides the memory?
MIL-STD-1553 transceiverThe slightly smaller dual-cavity DIP package, above the dual pulse transformers in the bottom-right corner, is a dual transceiver for the MIL-STD-1553 serial bus: each cavity has one transceiver. The MIL-STD-1553 bus uses high voltages (>20V, "high" by signaling standards) and differential signaling for noise immunity in military and aerospace applications (imagine a radar transmitting nearby and all the wiring picking up the stray sidelobe emissions), and was standard for a long time on aircraft and spacecraft. This one's a standard part, yet again made by UTMC:
Ken did a great writeup about the circuitry and various functions on the die:
https://oldbytes.space/@kenshirriff/112198313439124398 You can see the power transistors used as transmit drivers, as well as the laser-trimmed resistors used for differential reception.
Other diesThe 54FCT139 decoder which selects the EEPROM chips turns out to be more interesting than would be expected - it's implemented as a (very small) standard-cell gate array, rather than a purpose-built chip as is common with standard digital logic:
See
Ken's writeup on this for more details.
AT28HC64 EEPROM:
HA720 diode array, used to protect some external I/O:
54HC244 buffer, for either driving or receiving external discrete I/O signals:
54HC14 Schmitt-trigger inverters, either for external inputs or as part of the reset/watchdog logic:
Home
Help
Search
Login
Register
