Okay.

Here's the result and my analysis of the logic testing:

XOR A
OUT (AY_LATCH),A ; Clear register 0
psgrl_test:
1 LD A,$10 ; Value = $10
2 OUT (AY_WRITE),A ; Write $10 to register 0
3 IN A,(AY_READ) ; Port = RSEL/RD
4 LD A,$11 ; Value = $11
5 OUT (AY_WRITE),A ; Write $11 to register 0
6 IN A,(AY_READ) ; Port = RSEL/RD
7 JP psgrl_test ; Loop
The above logic analyser trace was produced using the above code (line numbered for ease of reference).
I have an 8-channel logic analyser, so I have restricted the data bus analysis to the lower 5 bits and the values used in the test accordingly, so I can record BC1, BDIR and ~WR (direct from the Z80) as well.
The first LOW in WR is line 2 of the code. BDIR goes HIGH, BC1 remains LOW for a WRITE operation to the PSG. The value on the data bus is 0x10, as loaded into the accumulator in line 1.
Line 3 executes a READ operation on the PSG, signified by the LOW on BDIR and HIGH on BC1. The value read on the data bus is 0x10, which is correct.
The next LOW on WR is line 5 of the code. A WRITE operation SHOULD be executed here, but it is not – BDIR remains LOW. The data bus correctly contains the value 0x11.

So it's obviously performing a write to receive the first value of 0x10, and returning that value on a read, but when I try to write an odd value BDIR doesn't go high to signal a write to the PSG's register.
I can't see how DQ0 (D0) would interfere with BDIR. The BDIR line from the 7402 (where WR is NOR'd with the chip select) doesn't go anywhere near DQ0 on the PCB!

Here's a gratuitous snapshot of the relevant (I hope!) part of the schematic:

EDIT: Something else I just noticed - there's no corresponding RD transaction after the attempt to write the odd value, either!