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Beating a Pendulum Clock

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--- Quote from: jpanhalt on October 17, 2021, 11:24:52 am ---@Zero999
Hello.  Long time since we shared experiences on ETO with your former alias.
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Yes, I remember you. I was banned from there around 12 years ago, along with many others who fell out with the administrator. The problem was the forum got trolled by lazy students asking for complete assignments. Myself and many others told them to bugger off, which was interpreted as bullying by some of the overly PC ETO staff and we faced disciplinary action. How's ETO nowadays?

--- Quote ---Yes, there are ways to use the other half of  the LM393, but in this approach, it was critical to have a non-retriggerable one-shot.   The MAX9814 offsets its output about 1.25V to avoid needing a dual supply.  The output voltage oscillates around that offset, and I wanted to time from the first rising edge.  That still created an uncertainty, but it is relatively small compared to the period of 1 second.

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I was thinking about something like this. The time delay is equal to R1*C1. In the stable state, the output is low and C1 is uncharged. When U2's inverting input is taken below 37% of the supply voltage, its output pulls one side of C2 to 0V, taking U1's -input below 0V, by 0.7V, as it's clamped by the PNP transistor in the input stage. U1's output will go high, charging C1 via R1 and R4, causing the +input to be higher than the -input. When C1 charges by one RC time constant, i.e. 63% of the supply voltage, the voltage across R1 will drop below 37% of the supply, U1's output will fall to 0V and discharge the rest of the voltage on C1, via D1. You could probably omit D1 but it's a good idea to include it, as there's a risk the current through the PNP input stage could be too high.

The circuit is non- retriggerable and is edge triggered. R7 is such a high value, the voltage on U1's -input barely changes, when U2 goes high and discharges C2. Any further pulses, whilst the output is high are ignored, because U1's -input will be lower than its +input, whist C1 is charging. If the trigger pulse is longer than the delay, the output will still go low, at the end of the time delay.

The trigger threshold will be about 1.85V, when operated off a 5V supply, a little higher than 1.7V, but probably acceptable.

R2 & R3 will alter the trigger threshold, but also the delay, so it's no longer = RC. Another potential divider could be connected to the +input to U2, to set the trigger threshold independently.


I have been playing with this project a little in between my other chores to get ready for Winter.  It seemed obvious that "capture mode" would be the way to go.  That does work well on a 16F1829.  One needs to shut off the comparator/capture after the first rising edge or capture is exercised several times for each beat.  However, I was committed to using that chip's little sister, the 12F1840.  Unfortunately CCP and C1OUT share the same pin.  I could not get it to work.  Moreover, there weren't enough appropriate pins for that plus serial out,oscilloscope out, and the comparator input.  So, I went with a simple stop TMR1, read, start routine.  That adds very little error.  Attached is the "final" schematic and code for the 12F1840.

While the numeric display is interesting, I found it not as helpful as the graphical display on the oscilloscope.  The clock works are open and small movements and breezes affect the pendulum.  The graphic display allows one to identify easily those disturbed ticks and tocks.  A clock mechanism in its case might not show such variations.  I decided not to mess any further with the numeric display/math.  The code as posted simply reports the 16-bit TMR1 counts in hexadecimal.


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