Effect of Clock Jitter on ADCs' SNR

[palpurul]

Hello,
I am researching high-speed/high-resolution ADCs and I learned that ADCs require low jitter clocks to preserve SNR. SNR degredation is specified by the famous formula which is given below
SNRJITTER = –20log ((2π) • FIN • TJITTER)

Fin: input signal frequency
Tjitter: Clock jitter + apeture jitter (or sqrt(Clock_jitter^2+aperture_jitter^2)

I assumed clock jitter in the formula is RMS jitter not peak-to-peak (Period jitter). Is my assumption correct?

Thanks!

[Doctorandus_P]

Just go back to the roots.
Imagine an ADC with a 0DBFS sine wave at it's input.
Zoom in at the zero crossing of the Sine.
If a sample is too early, or too late, you will sample a too low or too high voltage.

If you do this on a piece of paper, you instantly see the relation between time jitter and measured signal noise.

I do not care if you want to measure those errors in peaks, RMS, or potatoes.
You should be able to do that yoursef if you know what your units mean.

[ogden]

There are some useful appnotes around from AD, LT and Maxim. Just random internet search hits, yet giving answer to your question:

https://www.analog.com/media/en/technical-documentation/application-notes/AN-756.pdf
https://www.analog.com/media/en/training-seminars/tutorials/mt-007.pdf

[asgard]

From an app note from Analog Devices:

The relationship between SNR and jitter is given by this equation:

<fig1>

Maximum SNR vs Clock Jitter
Where fin is the frequency of the input signal, and tj is the jitter of the clock. The equation shows that for a high frequency input signal and a fixed amount of jitter the maximum SNR will decrease. This is because a faster slewing signal will have more of a voltage error with a given amount of jitter:

<fig2>
 
For input signals that have relatively low frequency content, under 1MHz lets say, the clock jitter becomes less critical, but when the frequency of the input signal is several hundred megahertz the jitter on the clock will be the dominate source of error, and will be the limiting factor for SNR.

Here is an easy chart that shows how SNR degrades with input frequency and jitter from the clock:

<fig3>