It seems like the bottom npn transistors are used as current source loads but how are the current values chosen for each stage?
I thought that the current source values would be chosen such that the output of the two amplifiers would be ~0V when the input is 0V.
However, I'd assume that the bias currents would also have an effect on the bandwidth of each stage? I'd really appreciate any kind of input on how circuits like these are biased for applications where bandwidth is also important. It'd also be great if someone could explain the circuit that's attached or how it should be analyzed. Thanks!
It seems like the bottom npn transistors are used as current source loads but how are the current values chosen for each stage?
You are correct they are current sink active loads for the respective transistors.
Choice of current is going to be based on having enough current to overcome any capacitance (intrinsic device, stray, next stage input) at the frequencies in question and also by the input impedance of the following stage (probably 50 ohms). For this kind of wide bandwidth circuit you'll generally throw as much as you can at it, but no more than you need to get the output impedance low enough to happily drive about 50 ohms impedance (and here we are definitely dealing with impedance as opposed to resistance and we must take capacitances into account).QuoteI thought that the current source values would be chosen such that the output of the two amplifiers would be ~0V when the input is 0V.
That's taken care of by the DC control loop set up by the preceding op amp, that you've omitted in your diagram. You can, however, still see the negative feedback limb of that being taken off from the output node. The DC input bias at the JFET gate will probably only be within a 100mV or so of zero, the op amp will take care of setting that at the right level for the output to be ~0V.QuoteHowever, I'd assume that the bias currents would also have an effect on the bandwidth of each stage? I'd really appreciate any kind of input on how circuits like these are biased for applications where bandwidth is also important. It'd also be great if someone could explain the circuit that's attached or how it should be analyzed. Thanks!
The 3k01 and 2k resistors from ground to -5 form a voltage divider. This sets the VBE of the two BC349 active load transistors (in combination with the 249 and 75 ohm emitter resistors) and hence sets the emitter currents to ~5mA and 15mA respectively.
From there, the top two transistors are a source follower and an emitter follower (connected very much like a Darlington pair would be) to provide masses of current gain and a voltage gain very close to one. Hence the impedance converter tag, very high input impedance (input DC bias current in the 10 pA region) and low output impedance (typically low enough to comfortably drive 50 ohms or thereabouts).
Most of the bandwidth comes from choosing source/emitter followers, which isolates drain/collector capacitance and avoids the Miller effect and just making sure that there's enough current drive at each stage to overcome intrinsic and stray capacitances.
A quick fiddle with SPICE shows the DC input impedance at the gate of the JFET to be 725Gohm, the DC output impedance to be 3.35 ohms at the emitter of the BTH10, and the overall DC voltage gain to be 0.93, all unloaded.
Thanks for the awesome response! I have a few more questions if you don't mind. When you talk about overcoming the intrinsic and stray capacitances, is it in the context of having to charge these capacitances at high frequencies? I'm assuming that if we don't have enough current then we might hit a slew rate limit like problem where we can't charge these capacitances fast enough to follow the signal? So this is why we want to throw as much current at it as we can so that we are covered in that regard for the most part?
Also I understood the calculations for how the BJT active load current is set, but how did you go about finding the effective output impedance of the amplifier? And once again thanks a lot for your response. It was really helpful in terms of getting a few things to click in my mind.
Pretty much. As soon as you get significantly above DC you pretty much have to think in terms of impedance as opposed to resistance, so there's always a reactive component to think about. As you surmise, the reactive part can have a significant effect on slew rates or just appear as a significant load. At 100MHz a stray 5pF to ground (a not unrealistic figure for say an amplifiers input capacitance) looks like 320 ohms to ground, or alternatively 3mA for every volt you try to impress across it.
I let SPICE* do the heavy lifting for that but it's not too difficult to work out by hand. An attempt at a tutorial here would get very long winded, very quickly. Hit your textbook of choice for the details; if you don't have a favourite I (and many others) would recommend "The Art of Elecronics" by Horowitz and Hill.
By the way, a search for "Signal Conditioning in Oscilloscopes" by Steve Roach will turn up a paper on impedance converter design that you'll probably find interesting and helpful - it's an easy read.
I went back and read the chapter where the JFET source follower is discussed in detail in The Art of Electronics and it was very helpful. I wish we had more info from the authors/publisher on the status of the "x chapters". The book briefly mentions that the source follower design with bandwidth and capacitive loads in mind will be discussed in chapter 3x.
The chapter by Steve Roach was the first place where I learned about the split AC and DC path architecture for the impedance converter. One thing that I found very interesting was that he talks about using depletion mode MOSFET rather than a JFET for the source follower due to its higher speed (higher ft?). Every DSO analog frontend schematic that I've seen seems to use JFET which seems to go against what Steve mentions in his chapter.
I'm also interested in your take on the higher end of bias current for both the source and emitter follower. I'd imagine that the top end limit of the bias current of the JFET would be the Idss since the JFET can't conduct more current than that. Is this the right assumption? As for the BJT emitter follower, I still don't have a good idea on how you would define the upper limit if power consumption of the circuit in general was being disregarded.
I've also noticed that most of the schematics I've looked at don't have the 100 ohm resistor (R6) before the input of the JFET. However, when I remove it the output frequency response doesn't really make sense.
If I fix the load at 50R the largest bandwidth loss looks like it's through J1.