Hoping for peer review of schematic.

[ioncoder]

I am new to electronics and am designing a circuit based on ESP32 for a project (Really enjoying the process). For the time being I have just added the ESP32 components so I have something to build the rest of the project around.

I am not sure if this is the correct place, but was wondering if someone could give constructive feed back on any mistakes I might have made or improvements I could make.

Many thanks

[inse]

The LEDs are reversed

[ioncoder]

Thank you, that was a silly mistake.

[ledtester]

On the CH340... what is the point of C12? The GND pin of the CH340 should just be connected to GND.

Also, the R232 pin can (and probably should) be left unconnected if you're not using it -- it is pulled down internally.

The 100K resistors R7 and R8 are very large. 10K is a more appropriate value.

The whole circuitry around the UART-DTR and UART-RTS doesn't match what you see in other ESP32+CH340 schematics (of which there are many examples on the web).

Did you use AI to create this schematic?

[ioncoder]

I did use AI, given I have no training in Electronics, it would have been overwhelming otherwise.

Thank you so much for the feed back, I will look for resources as you pointed out.

[bson]

You have DP/DN on the UART right next to the USB connector?  Why not draw it like a normal schematic so people don't have to hunt for what connects where?

A proper schematic rather than this maker shit should be a requirement to ask for feedback.

[ioncoder]

I didn’t ask for feedback, I asked for “constructive” feedback. I’ll consider your point though and decide if it’s the way I want to go.

[aeg]

bson's comment was tactless but in my opinion it's right.

Matters of style: GND always points down, power always points up. USB power net is always called VBUS.

You have two bulk decoupling capacitors on +3.3V, C1 and C6.

You have two bulk decoupling capacitors on VBUS, C3 and C11. The 20uF total violates USB maximum capacitance across VBUS specification.

I'm not sure what's going on with the diamond symbol between ESP32-EN and UART-RTS? Same for UART-DTR and ESP32-GPIO0.

There are two pullup resistors on ESP32-EN, R1 and R6.

One reason bson's comment is on point is because the stylistic issues in the schematic are so distracting that it's difficult to review it for circuit correctness.

[temperance]

One reason bson's comment is on point is because the stylistic issues in the schematic are so distracting that it's difficult to review it for circuit correctness

What is going on with the pull up resistors in the auto program "block"? Why aren't they connected with some lines instead of net labels?

-There is more than enough space on the page to draw the schematic with almost no net labels.
-You don't need those rectangles around functional blocks. It is a better choice to spend time on drawing the real connections for things which belong together. It is very hard to see that what those two transistors in the lower left do. They seem to belong to the block called UART (which should have been called RS232 interface) while they both connect to the same ESP pins.

If you are a programmer: net labels are like Go To's in software. Hard to decipher.

[pcprogrammer]

I didn’t ask for feedback, I asked for “constructive” feedback. I’ll consider your point though and decide if it’s the way I want to go.

Well it is constructive that some of the posts here are writing about the crap style used to draw the schematic. Unfortunately this style is creeping in big time and yours is even worse due to basic mistakes like how ground and power are drawn. Member aeg pointed this out and it would make a way better readable schematic if these rules where uphold.

And you did ask for a peer review, which you are getting. Best not to be snotty about it when you get negative feedback.

Net names / labels or net ports does not make that big a difference in my opinion, but with a simple schematic like this one using wires is even better. Combined with a net name makes it easier while drawing the PCB, because the trace name will make more sense.

Another remark on the readability of the schematic is that overlapping texts don't help either.

I'm not sure what's going on with the diamond symbol between ESP32-EN and UART-RTS? Same for UART-DTR and ESP32-GPIO0.

These are EasyEDApro's way of connecting two nets together. In the schematic the net "ESP32_GPIO0" and "UART_DTR" are connected to each other, and EasyEDApro can't handle this and uses that diamond shape to make the connection. In the netlist it will only use one of these names.

On the subject of that there is an error there anyway. The base of Q1 is driven by UART-DTR and the collector is pulling ESP32_GPIO0 low, and with these two signals directly connected to each other it won't work. The same applies for UART-RTS.

It is clear that you are a beginner, and my advice is to first learn a bit more about electronics before attempting something like this. Also learn more about drawing schematics and how the tools you are using work.

Certainly do not fall for using Artificial Intelligence to make up a circuit for you. Unless you know what you are doing, it is a recipe for disaster.

[ioncoder]

Thanks for the constructive feedback on the over use of Net Labels. I am a programmer and I can totally see what your saying. It looked good when I was doing it, to use another programmer term, I saw them as functions rather than goto statements, but I totally get your point. Net Labels probably have their use, but in this case they are not necessary for such as small circuit.

The diamond symbols are an outcome of my over use of net labels. I built the circuit with EasyEDA. You can't have two net labels on the same line without separating them with a short (diamond).

I think I am going to limit myself to including dev components in my circuits like a ESP32 Dev Board in a header socket, rather than trying to build my own out of discrete components.

If I need any more help, I'll pop back.

[bson]

One reason bson's comment is on point is because the stylistic issues in the schematic are so distracting that it's difficult to review it for circuit correctness.

The bigger problem is the piecemeal drawing.  If you want to, for example, review the use of the UART's modem control signals you can't just look and see where they're connected.  You have to exhaustively search the schematic for the appearance of the labels and then mentally connect them.  There's a reason we draw wires to indicate connections!  Combine this with the fact that it's just labels randomly dropped here and there, not even global labels with connection points.  This exhaustive search gets exceedingly tedious, and it's solely because of the OP's laziness in refusing to make a proper schematic - one that actually uses wires for connections, not just local labels.  [Edit: or lack of experience] Global labels here and there, or buses, to connect sheets or subcircuits is fine, like power symbols, but that's not what I'm looking at.  The absolutely only use for a schematic like this is to layout a PCB, where the schematic itself serves no real useful function other than to create the netlist.  But such a schematic shouldn't be put up for review as it's ephemeral and just pro forma trash.

Edit: don't really want to rail on OP here... it's more about this kind of schematics becoming ridiculously prevalent, you see them commonly, and I do understand OP is just mimicking what he's seen.  I'm more railing against this terrible practice in general.

[bson]

Thanks for the constructive feedback on the over use of Net Labels. I am a programmer and I can totally see what your saying.

[abeyer]

On the subject of railing against bad practices...

Am I the only one who finds both the terminology and practice of asking for "peer review" of AI slop pretty distasteful? At a bare minimum, even if you must do so, it seems disingenuous to not be very clear from the outset of what it is. Proper peer review is as much or more about building a shared model/culture of learning and understanding, when you remove the human it starts to feel more like just a request for free labor to proofread and correct the LLM's mistakes. I feel like it's disrespectful of people's time and willingness to help if you aren't making it clear what you ask for.

[pcprogrammer]

I agree with that this kind of schematic is basically only good for routing a PCB, but even as such there is a big risk of errors, that can be avoided by making a proper one.

But with pressure on delivering something corners are cut and this kind of crap rolls out. With the use of AI it only gets worse, since that has been feeding on this kind of crap because it is all over the internet. Just take a look at the schematics of a lot of development boards. It is net labels and ports around the clock plus the neatly squared of small pieces of the puzzle nicely labeled with an indication of what it is, as if it was not clear from the part itself already.

Also the IC layout box style used for components. The pins in perfect order as on the actual device without taking into account what their function is. Or even worse, and I admit to do this myself to for the ease of it, use the same style for logic that has well defined symbols, but that makes it harder to allow for the power pins. It does take more knowledge of the EDA tools used to make up a proper set of symbols for for instance a quad nand gate.

But it makes a schematic way more readable if the proper symbol is used.

I also agree with abeyer that it is kind of disrespectful to present AI generated crap and then ask for help on it. But it is part of the kind of lazy world we are living in. Doing due diligence is vanishing.

You can't speak of "peer" when you are not on the same level, so not even correct in this case. "senior review" or "master review" is more appropriate.

[NE666]

"senior review" or "master review" is more appropriate.

"Unpaid consultancy" also comes to mind.

[PGPG]

You have to exhaustively search the schematic for the appearance of the labels and then mentally connect them.

Trully.. You don't have to
I have opened that schematic and closed it at once.
If someone draws schematic in a way readable only to him and to computer program then I will not loose my time on it. It is his decision if he needs human help or not.