Bipolar square voltage generation

[ikkaru]

Dear All, I'm new to the platform. Please advise if I'm doing something against the norms.

I want to generate bipolar square pulses (1-7Hz but pulse width of 30ms) of variable voltage (1-12V). The load current can go up to 1A. I want to trigger pulses with a TTL signal (from a Microcontroller). I need the pulses with reference to a ground (GND). To my understanding, an H-bridge will not provide the signal w.r.t to a GND. Thus, I was thinking of using the circuit below. I'm new to practical electronics. Your ideas and any leads will be highly appreciated.

[Zero999]

That will subject the MOSFETs' gates to excessive voltage. They're generally rated to 20V or less and that circuit subjects them to 24V.

Where is the power coming from? You'll need some sort of voltage regulator to reduce the 12V down to a lower voltage.

Any why? What's the application?

[BrokenYugo]

The term you're looking for is "push pull" output, you're on the right track but the control side needs work as Zero999 outlines.

https://en.wikipedia.org/wiki/Push%E2%80%93pull_output

[moffy]

1. Remove the pull up resistor to +12V on TTL1, you don't want to overload the TTL output.
2a. Swap the inputs on TTL1 comparator so that TTL1 with a pull down to gnd goes to the -ve input and the voltage divider goes to the +ve input, this will ensure for no input the +ve MOSFET is off.
2b. Add some hysteresis around both comparators.
3. I assume that the +/-12V to the MOSFETs are variable and separate to the fixed +/-12V to the comparators.
4. You need to set the threshold about half way between the TTL high and low: for TTL that's about 1.2V, for 5V CMOS it's 2.5V for 3.3V CMOS it's 1.65V.
5. Put a resistor in between the comparator output and the MOSFET gate, say 5k.
6. Put a 12V zener between each gate and source, properly oriented.
This isn't the best configuration but fixes most of the problems with your circuit, but I can't guarantee it will work, and there is always the chance of turning both MOSFETs on at the same time and creating a short circuit.

[ikkaru]

That will subject the MOSFETs' gates to excessive voltage. They're generally rated to 20V or less and that circuit subjects them to 24V.

Where is the power coming from? You'll need some sort of voltage regulator to reduce the 12V down to a lower voltage.

Any why? What's the application?

Initially, I was thinking to use a LM317 and change the main power (12V) to this circuit from 1-12. Now I feel stupid that I thought that way. The gates will not work in the low voltages, even if I go for logic level FETs. I will follow moffy's advice and use variable voltage to the mosfets. I guess it could work.
The application is a mygraphic pacer, i need to build a pacing device for a biology project. Usually these pacers are operating on higher voltages. But in my case we are pacing cells, so the voltage should be low. The load is a small (1ml) saline cup with two gold electrodes in it. So it will have a resistive and capacitive components to it.

[ikkaru]

The term you're looking for is "push pull" output, you're on the right track but the control side needs work as Zero999 outlines.

https://en.wikipedia.org/wiki/Push%E2%80%93pull_output

Thanks a lot for the lead. Your term nails it. 😃. Now my search is filled with relevant circuits.

[ikkaru]

1. Remove the pull up resistor to +12V on TTL1, you don't want to overload the TTL output.
2a. Swap the inputs on TTL1 comparator so that TTL1 with a pull down to gnd goes to the -ve input and the voltage divider goes to the +ve input, this will ensure for no input the +ve MOSFET is off.
2b. Add some hysteresis around both comparators.
3. I assume that the +/-12V to the MOSFETs are variable and separate to the fixed +/-12V to the comparators.
4. You need to set the threshold about half way between the TTL high and low: for TTL that's about 1.2V, for 5V CMOS it's 2.5V for 3.3V CMOS it's 1.65V.
5. Put a resistor in between the comparator output and the MOSFET gate, say 5k.
6. Put a 12V zener between each gate and source, properly oriented.
This isn't the best configuration but fixes most of the problems with your circuit, but I can't guarantee it will work, and there is always the chance of turning both MOSFETs on at the same time and creating a short circuit.

1. Understand. Will do that.
2a. I get it. Will follow.
2b. Let me read on that. Not familiar with the term.  PS: I guess you are referring to the voltage difference between the logic levels.
3. I was initially thinking otherwise. Now I understand this is the way to go. Thanks.
4. Got it. I am using 5v TTL, will set the threshold accordingly.
5. Understand. I think its for limiting the high currents from the capacitive components.
6. Okay. Is that for any voltage spikes that can occur?

Thanks a lot for the informative response. Can you suggest a better way that I accomplish the task? If you could give me some keywords on it, I will read and draw an upgraded version. Thanks again.

[moffy]

1. Remove the pull up resistor to +12V on TTL1, you don't want to overload the TTL output.
2a. Swap the inputs on TTL1 comparator so that TTL1 with a pull down to gnd goes to the -ve input and the voltage divider goes to the +ve input, this will ensure for no input the +ve MOSFET is off.
2b. Add some hysteresis around both comparators.
3. I assume that the +/-12V to the MOSFETs are variable and separate to the fixed +/-12V to the comparators.
4. You need to set the threshold about half way between the TTL high and low: for TTL that's about 1.2V, for 5V CMOS it's 2.5V for 3.3V CMOS it's 1.65V.
5. Put a resistor in between the comparator output and the MOSFET gate, say 5k.
6. Put a 12V zener between each gate and source, properly oriented.
This isn't the best configuration but fixes most of the problems with your circuit, but I can't guarantee it will work, and there is always the chance of turning both MOSFETs on at the same time and creating a short circuit.

1. Understand. Will do that.
2a. I get it. Will follow.
2b. Let me read on that. Not familiar with the term.  PS: I guess you are referring to the voltage difference between the logic levels.
3. I was initially thinking otherwise. Now I understand this is the way to go. Thanks.
4. Got it. I am using 5v TTL, will set the threshold accordingly.
5. Understand. I think its for limiting the high currents from the capacitive components.
6. Okay. Is that for any voltage spikes that can occur?

Thanks a lot for the informative response. Can you suggest a better way that I accomplish the task? If you could give me some keywords on it, I will read and draw an upgraded version. Thanks again.

Hysteresis is to stop the output of the comparator from jittering or rapidly switching when near the switching threshold. It involves placing a resistor from the output to the +ve input, but read up on it as it is a little more involved.
The output resistor and zener diode are to clamp the maximum voltage from gate to source at 12V regardless of the output voltage supplies.
You should always ensure that there is a deadtime between switching one transistor off and the other on so that they are never on at the same time. Switching takes a finite amount of time and you should ensure that the off transistor is fully off before turning the other one on.
For a better way use a standard H bridge driver/H bridge and some isolation e.g. opto couplers between the MCU and the H bridge. The isolation will help protect the MCU and provide easy level shifting.

[ikkaru]

Hysteresis is to stop the output of the comparator from jittering or rapidly switching when near the switching threshold. It involves placing a resistor from the output to the +ve input, but read up on it as it is a little more involved.
The output resistor and zener diode are to clamp the maximum voltage from gate to source at 12V regardless of the output voltage supplies.
You should always ensure that there is a deadtime between switching one transistor off and the other on so that they are never on at the same time. Switching takes a finite amount of time and you should ensure that the off transistor is fully off before turning the other one on.
For a better way use a standard H bridge driver/H bridge and some isolation e.g. opto couplers between the MCU and the H bridge. The isolation will help protect the MCU and provide easy level shifting.

Thanks for the  quick response. I will further read on the Hysterisis. This should be a fine start. Understand about the deadtime. There will be atleast a 0.2second deadtime between alternate pulses.

My initial issue with using an Hbridge was that I wanted to get the biphasic pulse with reference to a ground. I assume Hbridge does it without a dual power supply. I thought if I wanted to push one output terminal to the ground, i have to float the whole Hbridge and MCU circuit in an isolation transformer secondary (may be the supply transformer itself). I thought that way can cause EM issues as most of the circuit is not connected to the ground, but only the output. But let me try to put that on paper and think again.

[pqass]

Consider swapping N-FET/P-FET positions; where FET sources are tied to the output, not supply.  That way the +12V to -12V swings will be within the usual +/-20V Vgs limits (like the IRF540/IRF9540); forgoing zeners to protect the gates.

Also, use of op amps vs. open-collector comparators is likely fast enough for your application and further eliminates the required pullups.  Virtually any op amp (non rail-to-rail, eg. 741, LM358) will do as long as its supply range is >30V.

You can then use an [individually] variable bipolar LM317/LM337 supply for the FET drains. However, since there is a ~1.5V voltage drop, you'll likely need to bump up the FET supply/op amp supply to +/-15V to guarantee a +/-12V output..

See simulation here and attached screenshot below.

[ikkaru]

Consider swapping N-FET/P-FET positions; where FET sources are tied to the output, not supply.  That way the +12V to -12V swings will be within the usual +/-20V Vgs limits (like the IRF540/IRF9540); forgoing zeners to protect the gates.

Also, use of op amps vs. open-collector comparators is likely fast enough for your application and further eliminates the required pullups.  Virtually any op amp (non rail-to-rail, eg. 741, LM358) will do as long as its supply range is >30V.

You can then use an [individually] variable bipolar LM317/LM337 supply for the FET drains. However, since there is a ~1.5V voltage drop, you'll likely need to bump up the FET supply/op amp supply to +/-15V to guarantee a +/-12V output..

See simulation here and attached screenshot below.

I dont know what to say 😅. You all are amazing. I have been using LTSpice for some simulations I did. Never checked the possibility of online simulators. Your solution seems better than I proposed. And yes, i will go with the LM317/337 dual power supply and maybe use a +/-15 input to reach the desired outputs. I think i will also prototype your version with some 741 opamps and share the result.
Thanks again for going the extra mile for helping others.

[dobsonr741]

Driving with 741: the opamp slew rate might be too slow when you driving with MCU output into the opamp input. Easy to simulate. As the result, you’ll see the dead time disappear and both MOSFET will conduct. Add an RC to drive the opamp with a ramp instead of fast square wave, so the window comparator can still give you the dead time, even with a 741. Rule of thumb the slew rate after the RC, on the input should be slower that 741 slew rate, 0.5V/us

[pqass]

Further to my simulation circuit...
I have just one 5Hz TTL source. But instead of driving each opamp +in from its own GPIO (and thus having to code for dead time), you can instead have a 150K/100K divider (for CMOS GPIOs) between both GPIOs whose center feeds both op amp +ins.
Why?  That way, your code can just issue the following and leave the 330n cap to manage the dead time:
 PORT=0x03;     for +output,
 PORT=0x00;     for -output, and either
 PORT=0x01; or
 PORT=0x02;     for no output (disconnected from +/- supplies) since that would produce 2.0V which sits between upper and lower ref signals (+2.5V/+1.7V).  And no danger of enabling both FETs at the same time.

One down-side is that on initial power up, your GPIOs might default to inputs and therefore +ins are floating. Maybe add a parallel 1.5M/1M divider from +5V/0V, center feeds the +ins?

The downside for using cheap slow op amps is that they will take time to transition a FET from on to off, and vice versa.  That just means more heat during the transition (vs a faster op amp). But at 12W (12V @ 1A) may be inconsequential.

[Zero999]

Consider swapping N-FET/P-FET positions; where FET sources are tied to the output, not supply.  That way the +12V to -12V swings will be within the usual +/-20V Vgs limits (like the IRF540/IRF9540); forgoing zeners to protect the gates.

Also, use of op amps vs. open-collector comparators is likely fast enough for your application and further eliminates the required pullups.  Virtually any op amp (non rail-to-rail, eg. 741, LM358) will do as long as its supply range is >30V.

You can then use an [individually] variable bipolar LM317/LM337 supply for the FET drains. However, since there is a ~1.5V voltage drop, you'll likely need to bump up the FET supply/op amp supply to +/-15V to guarantee a +/-12V output..

See simulation here and attached screenshot below.

I dont know what to say 😅. You all are amazing. I have been using LTSpice for some simulations I did. Never checked the possibility of online simulators. Your solution seems better than I proposed. And yes, i will go with the LM317/337 dual power supply and maybe use a +/-15 input to reach the desired outputs. I think i will also prototype your version with some 741 opamps and share the result.
Thanks again for going the extra mile for helping others.

Sorry, that won't work, because the MOSFETs don't have enough drive, when the output voltage is set high. It'll also subject the gates to over voltage in a similar manner to the circuit posted at the start of the thread.

Simulators are great. I use them a lot, but quite often I don't bother because there aren't always good models for them.

How about using an audio amplifier?

The LM1875 can be used as a high power amplifier.
https://docs.rs-online.com/5fc4/A700000009184665.pdf

U2 is generic op-amp and is configured  as an inverting or non-inverting amplifier, depending on whether M1 is turned on or not.

Don't get me wrong, the original circuit, but with zeners and the MOSFETs powered from an LM317/LM337 will work. I just wanted to post a completely different way to do this.


EDIT:
Rough LTSpice simulation attached. I've just used generic models and skipped the voltage adjustment potentiometer. It's just to illustrate the concept works. There might be more or less overshoot in real life. It might be necessary to introduce some RC circuits to slow it down.

[MarkT]

Perhaps a bipolar DAC into an opamp with high current buffer in the loop is a clean approach, and not limited to bipolar square waves either.

[Neomys Sapiens]

You can also find ready-made circuits for your application in the output stage of several 'hobby lab' pulse generator projects. They typically allow to control the voltage of the Low- and High-Level of a logic level input signal independently. Some of them allow even to control through 0V, for example -15...0...15V.
Sources publications Elrad, Elektor, Electronics and Wireless World, Popular Electronics, website EDN, several books...

[dobsonr741]

OP asked for 1A output current. It complicates things a bit, and calls for discrete MOSFETs. Did not have rise/fall time concerns, and frequency is rather low.

[BrianHG]

Why not use a SN75155 RS232 transmitter with it's output feeding a push-pull NPN/PNP emitter follower placing a resistor to GND at the output.  (Or if you want a floating disabled output, tie the resistor between base and emitter on the transistors)

3.3v or 5v logic input controls.
Output enable will will allow you to center your output\, or, if your have a resistor between the base and emiter, you can switch the output into high impedance.

Or, better yet, use a 2 channel RS232 transmitter, using each output to drive the gate of a N-channel mosfet to create your push-pull configuration with still a set of logic level digital inputs.

Ore, even better yet, why not just use a high-side/low-side push-pull mosfet gate driver IC designed for dual polarity outputs, disable mode for the outputs and logic level input control, with a built in boost converter for driving the high-side N-Channel mosfet gate.  With this guy, you have built in short-circuit protection which will prevent turning on both mosfets simultaneously shorting out your supply.

[Neomys Sapiens]

OP asked for 1A output current. It complicates things a bit, and calls for discrete MOSFETs. Did not have rise/fall time concerns, and frequency is rather low.

Indeed I overlooked the current requirement. Then again, a solution substituting power OPAs for the buffers used in some of those circuits could be made up.

[pqass]

Sorry, that won't work, because the MOSFETs don't have enough drive, when the output voltage is set high. It'll also subject the gates to over voltage in a similar manner to the circuit posted at the start of the thread.

Simulators are great. I use them a lot, but quite often I don't bother because there aren't always good models for them.

Yup. I see it now.  Any FET drain supply rail above 5V (or below -5V) will take away from the Vgs. As it goes below 10V Vgs, the FET will start to incurr more voltage drop (not fully on).  See attached; with a +12V rail producing a 1.1V drop on the upper FET due to 4.1V Vgs vs. lower FET being fully on with a -5V rail due to its 10V Vgs.

However, the gates (Vgs) never go beyond +/-14V.  See old simulation with voltmeters showing bad Vgs and FET voltage drops.

So we're back to the original (top)P-FET/(bottom)N-FET placement and therefore needing zeners to protect the gates.
I'm sure you can buy some specialized part that does this but part of the fun (for me) is solving for minimal BOM and use of generic components. 

See attached workable solution and new simulation. If an LM311 comparator is used, it adds just two resistors and a zener per half.  The LM311 can be configured two ways; collector output to +15V, emitter output sources current, or, emitter output to -15V, collector output sinks current.  The resistors chosen will guarantee they don't draw more than 18mA from the LM311 when the rail is +/-12V yet still provide at least 10V Vgs with a +/-1V rail.

The FET beta and threshold values (double-click on symbol) were updated to reflect IRF540/IRF9540 parameters.

[Zero999]

Another idea using an R-2R DAC.

It'll give +/- 12.7V in 100mV increments with an 8-bit digital input.

A to G are at first converted to 0 to 1.27V -1.27V by U2, a generic op-amp.

U1 again is the power amplifier, but this time its gain is set to non-inverting/inverting 10, depending on whether Q1 is switched on or not.

A to G are inputs which must be exactly 5V.  If the power supply to the MCU isn't that stable, use a buffer such as the 74HCT241, powered from a precision 5V reference.

The sign is positive, when the positive input is high and is negative, when low.


EDIT:
Q1 changed to a P-FET, because it's switching a negative voltage, when the gate voltage is 5V. It needs to have a low enough on resistance and cut-off voltage. The J176, or perhaps in a pinch the J175, will do.

[dobsonr741]

The power op-amp idea is very likable. I would use monolithic DAC instead of resistor ladder, like MCP4802/4812/4822 with an internal reference to simplify. There are a few good other power op-amp choices, like OPA541/549, just to name a few audio amp in op-amp disguise. Some has programmable current limit too.

[ikkaru]

OMG. I am going to read and grasp all these suggestions tomorrow first thing, and will definitely buy components for more than one method to test the real prototype outcome. Thanks everyone who are helping. The power opamp/audio amplifier idea never crossed my head. 

[Zoli]

Check the TDA2030(LCSC link). Attached is an idea to start.

[dobsonr741]

Lm1875/Lm675 seems to be a better part for this purpose than TDA2030. TI still ships original LM1758, while the 2030 will be a knockoff with who knows what quality, offset and thermal behavior at DC operating point. I’m not sure if OP is interested in lowest price and quality.