EEVblog Electronics Community Forum
Electronics => Projects, Designs, and Technical Stuff => Topic started by: Glenn0010 on November 07, 2017, 01:53:15 pm
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Hi all this is my first post here,
I am doing my final year thesis in electronics and control. I have built a prototype board for my BLDC motor controller. The board has a lot of test points and jumpers so I can manipulate components in and out of circuit to see what effect they have on the wave forms.
What I want to test for now is:
1. The effect of the electrolytic capacitor in parallel with the ceramic bootstrap capacitor.
2. The effect of the diode in parallel with the gate resistor
3. Effective Snubbing to have clean 'power' wave froms
Below are the schematics:
(https://i.imgur.com/xpgPBPv.png)
(https://i.imgur.com/qc2899U.png)
And here is my soldered board:
(https://i.imgur.com/uwXU4Kd.jpg)
I tested the functionality of all the FETs using a 10 Ohm load resistor. I put the probes across the load resistor and here are the waveforms I got:
(https://i.imgur.com/cWZL3nV.png)
(https://i.imgur.com/lDoNelP.png)
I measured the ringing frequency at around 13.2 MHz. I obviously want to eliminate this ringing and that nasty voltage spike. My FETs VDS is rated at 100V however I want to eliminate this.
I have read several papers and application notes on Snubbing and from what I understood and from the equations it seems that the voltage spike and ringing is to do with the stray inductances of the components traces etc (LLK).
I have used this AN from NXP as my main guide. https://assets.nexperia.com/documents/application-note/AN11160.pdf (https://assets.nexperia.com/documents/application-note/AN11160.pdf)
I do have some questions though:
1.Do I just need an RC snubber circuit across the high side FETS as the NXP AN seems to State?
As this document from TI seems to inidcate that the RC snubber should be placed across the low side FETs : http://www.ti.com/product/CSD88599Q5DC/datasheet/layout? (http://www.ti.com/product/CSD88599Q5DC/datasheet/layout?)
An I have found this source that indicates snubbers across both sides
(https://i.imgur.com/uWShPc5.png)
2.Could I get away with placing just 3 ceramic caps across each half bridge as I just have big fat electrolytics across the POWER rail which are useless for this kind of thing.?
Sorry for the questions but I am a bit confused.
+ Attachments and other options
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It looks like the layout might well be the cause of your issues, it is rather "loose" and spread out. The trace inductance between the gate driver and the fet will form a resonant network, which is one of the potential sources of your issues. The other is the stray inductance in the power section. As I can see straight through your board, I assume there is no ground plane, and your power traces meander about quite a bit too.
I suggest you read up a bit on power pcb design. The idea is to minimise trace inductance by keeping the "loops" short. Every current that flows in a conductor has to return to its source.
Inductance is influenced by a few major factors, length and area being the main ones. So to get low inductance we want to have a return path right next to, or underneath its source.
Since the return path is often ground a groundplane on the bottom or inner layers will provide a good path for most signals (provided it is not broken into many pieces by traces).
For other return paths, such as your high side drivers the same still applies, but your return path is now the bridge mid point.
Your schematic looks quite decent otherwise, though I would remove the jumpers for components you can just solder in as needed, such as the caps and diodes. This so you can squish stuff together tighter.
I would also add some MLCC caps to your bridge decoupling strategy, the electrolitics alone might not be good enough with regards to ESR and inductance.
Once you get all of this under control you can start to think about snubbing what is left of your resonance, but right now its a bit of a patch for a poor layout.
Oh, and a final note. Maybe test stuff with a current limited bench supply, not with what I assume is a RC lipo battery going by the vaporised trace ;). This saves on fireworks, better yet would be some current protection built in to the design, so faults in the load are covered too.
Edit:
As quick run through the numbers shows the 13ish Mhz is correct for the trace inductance you have in the power section. plugging some guesses for your board into there (3mm width, 9mm separation and 4cm length) gives 151nH your bridge output capacitance is 880pf (two fets), so that gives 13.8Mhz.
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It looks like the layout might well be the cause of your issues, it is rather "loose" and spread out. The trace inductance between the gate driver and the fet will form a resonant network, which is one of the potential sources of your issues. The other is the stray inductance in the power section. As I can see straight through your board, I assume there is no ground plane, and your power traces meander about quite a bit too.
I suggest you read up a bit on power pcb design. The idea is to minimise trace inductance by keeping the "loops" short. Every current that flows in a conductor has to return to its source.
Inductance is influenced by a few major factors, length and area being the main ones. So to get low inductance we want to have a return path right next to, or underneath its source.
Since the return path is often ground a groundplane on the bottom or inner layers will provide a good path for most signals (provided it is not broken into many pieces by traces).
For other return paths, such as your high side drivers the same still applies, but your return path is now the bridge mid point.
Your schematic looks quite decent otherwise, though I would remove the jumpers for components you can just solder in as needed, such as the caps and diodes. This so you can squish stuff together tighter.
I would also add some MLCC caps to your bridge decoupling strategy, the electrolitics alone might not be good enough with regards to ESR and inductance.
Once you get all of this under control you can start to think about snubbing what is left of your resonance, but right now its a bit of a patch for a poor layout.
Oh, and a final note. Maybe test stuff with a current limited bench supply, not with what I assume is a RC lipo battery going by the vaporised trace ;). This saves on fireworks, better yet would be some current protection built in to the design, so faults in the load are covered too.
Hey thanks so much for your reply.
I know my PCB design wasn't ideal. I needed those jumpers, so I can test the electrolytic bootstrap cap and the diode to see what difference they make.
Also I didn't include any power planes since I never worked with the UCC20520 before and wanted to make sure I got it functioning and I thought having no power planes would make it easier to troubleshoot had any faults occurred.
Is the magnitude of the ringing solely determined on the trace/package inductance? Or will the magnitude of the voltage spike be increased if I used a BLDC motor as a load?
My plan was to test these components and apply a snubber circuit. Then test again my old BLDC motor code for sanity and redisgn a proper, small low inductance PCB. However it seems that you think that I should start with that. Obviously I want to design as few PCBs as possible for costs etc.
I think a good compromise wold be to test the diode and electrolytic cap, test the code and make a proper pcb which will include the Uc as well. Then leave some pads on the PCB to calculate the scrubber?
Oh yeah I'm using an ebike 18650 pack as my supply as I don't have a proper supply at home. The idiot that I am I tried to measure the deadtime on the outputs and shorted the supply through the scope.
Thanks again!
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You need to realize that the need for RC snubbers in a hard-switching bridge circuit like that is often mainly to compensate for layout problems. Thus, the style of snubber used, and the value of components needed, are highly dependent on the layout. (Snubbers may also be needed to compensate for the nonidealities of the semiconductors, but because the layout probably dominates, you can't test that!)
So, normally you'd start by designing a proper layout - then adding snubbers as needed.
Your layout looks like a total catastrophe, sorry. On the other hand, this helps produce clear results on what kind of snubbing helps in this kind of "extreme", totally failed (sorry!) circuit design; but on the other hand, the implications cannot be directly used, since the style and magnitude of issues will be different.
Snubber components themselves need to be as low inductance as possible, making "socketing" or switching between them useless, because the extra inductance invalidates the practicality of the results. Thus, the only way is to lay the snubber components out properly - you'll need to desolder/solder them as you go, but that's not a big deal since you are probably not going to go through tens of different snubbers.
So, in my opinion, you are approaching this in the completely wrong way, exact opposite to what actually makes sense (and how it's normally done, too). While you may think that the layout is only "kind of" important, it's not; it's actually the meat here; all you are trying to measure and study is completely based on your layout!
Even if you accepted the poor power layout (which could make some sense, since you are trying to fix issue caused by it by using the snubbers, after all!), you'd need to do the snubber layouts as well as possible.
I know that learning about a good power layout may look like an overwhelming task, so let me give you a single tip which will lead you in the right direction: DC bus (your battery voltage) - think about it as two parallel plates, like a capacitor. If you insist on 2-layer design, then it'll be two wide (several inches, if you wish!) fills, one on the bottom layer, one on the top, with only the thickness of the board between them. Fill it with DC bus capacitors (using vias to connect to the "other side", there will be small cutouts then), going directly between the two "plates". This might not be the final or optimal design, but draw it, and your mindset will be in the right place, when you force yourself to add the semiconductors between these plates with almost negligible distance and hence, stray inductance.
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You need to realize that the need for RC snubbers in a hard-switching bridge circuit like that is often mainly to compensate for layout problems. Thus, the style of snubber used, and the value of components needed, are highly dependent on the layout. (Snubbers may also be needed to compensate for the nonidealities of the semiconductors, but because the layout probably dominates, you can't test that!)
So, normally you'd start by designing a proper layout - then adding snubbers as needed.
Your layout looks like a total catastrophe, sorry. On the other hand, this helps produce clear results on what kind of snubbing helps in this kind of "extreme", totally failed (sorry!) circuit design; but on the other hand, the implications cannot be directly used, since the style and magnitude of issues will be different.
Snubber components themselves need to be as low inductance as possible, making "socketing" or switching between them useless, because the extra inductance invalidates the practicality of the results. Thus, the only way is to lay the snubber components out properly - you'll need to desolder/solder them as you go, but that's not a big deal since you are probably not going to go through tens of different snubbers.
So, in my opinion, you are approaching this in the completely wrong way, exact opposite to what actually makes sense (and how it's normally done, too). While you may think that the layout is only "kind of" important, it's not; it's actually the meat here; all you are trying to measure and study is completely based on your layout!
Even if you accepted the poor power layout (which could make some sense, since you are trying to fix issue caused by it by using the snubbers, after all!), you'd need to do the snubber layouts as well as possible.
I know that learning about a good power layout may look like an overwhelming task, so let me give you a single tip which will lead you in the right direction: DC bus (your battery voltage) - think about it as two parallel plates, like a capacitor. If you insist on 2-layer design, then it'll be two wide (several inches, if you wish!) fills, one on the bottom layer, one on the top, with only the thickness of the board between them. Fill it with and DC bus capacitors (using vias to connect to the "other side", there will be small cutouts then), going directly between the two "plates". This might not be the final or optimal design, but draw it, and your mindset will be in the right place, when you force yourself to add the semiconductors between these plates with almost negligible distance and hence, stray inductance.
Thanks so much for the feedback! I knew my layout was a mess, ut I guess I did not realize how much of a difference it would make. So I shall abandon the scrubber design until I run the other tests, test my 6 step commutation code again and implement the SPWM in code. Then I shall design a proper board with the Uc included and proper layout.
1 Can I test the BLDC motor at 48V or will the added inductance of the motor produce even bigger voltage spikes and exceed the VDS of my FETS? or is it solely reliant on the stray inductance.
2 Do you have a recommendation on how to include the snubbers on the final board version. Snubber caps and resistors are fairly low in values typically so I can use the 1206 package. Shall I just place the footprints on the board for the final layout and the solder and desolder as needed?
PS do you think this is a good procedure ot go about things?
Thanks so much for the feedback! looking forward to improve this mess
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Add the motor but run at much lower voltage first to measure the spikes without blowing up the devices. Note that the actual spike can be higher than your scope shows.
Nothing prevents you from running at, for example, just 4-5 volts first. This also limits current by the winding resistance so that you can test if your active current limiting works before actually blowing anything up. At full voltage, the current through the winding resistance is so high that the fets will blow up instantly if your current sense doesn't react in a few hundreds of microseconds, and the motor inductance saturates. Ramp up the voltage, see how the spikes are at 10V. If they are at 20V, you can expect they'll be at least at 96V when 48V is applied. As a first-order simple guesstimate, at least :).
Really work on the layout. I have never used any RC snubbers in a motor control bridge, never found any need to use one. You can add some 1206 or even just 0805 package RC snubber over the FETs, as close as possible - but never compromise the layout by adding the snubbers.
As you are not manufacturing the PCB by yourself, there is no reason not to use 4-layer board. Once your layout is properly done, your board will be so much smaller that the 4-layer manufacturing isn't probably any more expensive than the 2-layer manufacturing currently is for you.
4 layers will give you a nice low-inductance top layer + mid1 (or bottom + mid2) pair to form the DC bus I wrote about earlier, the gap between the layers will be very small; and you'll still have two layers left so you can easily route short gate drive connections! Use a lot of vias when you need to jump between layers, both from the inductance & resistance viewpoint. Basically, I try to dedicate both mid layers as ground planes, only doing short traces in only one of them, since a motor driver won't have too many things to route.
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I guess I did not realize how much of a difference it would make.
The thing is to understand is that the faster you want to change the current that is flowing through any objected, the more that objects inductance matters! (for an inductor V = L di/dt, ie the voltage generated across that inductor (V) is proportional to the objects inductance (L) multiplied by the rate of change of current (di/dt))
The reason this REALLY matters for any switching circuit is that semiconductors would rather be fully OFF or fully ON, the bit in the middle where they effectively have some resistance is a bad area to operate in, because the loss across that semiconductor is massive. (when it's OFF, and no current flows, there is no loss. When it is ON, current flows, but it's resistance is tiny, so the losses are manageable, but when it is conducting current but with high resistance, it has a high voltage drop and so a massive power loss). Hence, all switching circuit designers have to make a trade off between fast switching as fast as possible to minimise losses (the fundamental frequency itself is not that important but what is important is the time it takes to switch from conducting to non conducting) and switching slower to avoid voltage spikes and EMC/EMI issues.
Consider a Switch with 10 amps flowing through it, when we turn it off, in say 1 microsecond. The rate of change of current, di/dt, is 10 amps / 0.000001 seconds, which is 10 MILLION amps per second! So even a tiny amount of stay or parasitic inductance, even in the nanohenries, will generate a significant voltage across it.
Your job as a circuit designer is to make the necessary design trade offs and find a suitable layout where you can switch your semiconductors at the rate you need to get to your efficiency or thermal performance targets. Poor layout with intrinisic inductance that cannot be designed out is often compensated for by slowing down the switching time of the switches (using larger gate resistors) but this increases the thermal loading, and reduces efficiency. In the worst case, you may have to de-rate your device to a lower current capability in order to prevent voltage overshoots and over heating.
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I don't have much to add to the above, sound advice.
As for your wanting to test the influence of certain parts, ask yourself why you would need them. Does the datasheet suggest them, or does the math say you need them? etc.
In prototyping its a good idea to leave some flexibility in the design, and gate drivers especially benefit from some extra footprints between them and the gate. But always keep in mind why you are doing what
you are doing, don't just try it. Do some back of the envelope math with rough guesses, or even a quick simulation to figure out what something should do . You might do the right thing for the wrong reasons otherwise, or get led down the garden path by a misunderstanding.
If you want some inspiration, have a look at the Vedder ESC, the design files are available as is the code as I recall. Notice how that design has current limiting for example that will save your fets/pcb from exploding, also the layout is compact. I'm not saying its the best possible BLDC solution, but it might be a good place to start taking inspiration from. Also have a look at app notes from the semiconductor manufacturers, they often have suggested layouts and schematics for their development boards.
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Yeah, having looked at your schematic again, it seems to lack current limiting. I was assuming it has it, without looking, since it's basically 100% mandatory.
Using a mosfet driver with a so-called "desaturation detection" will do well enough, or you can add separate low-side shunts and amplifiers.
But you need to measure current at some usable accuracy (such as +/- 50%) and be able to react to it in maybe about 50-100 µs. Otherwise a few wrongly calculated PWM cycles, and all your MOSFETs are dead -- and even good, tested algorithms cannot guarantee they can work out correct PWM cycle calculations without relying on current limiting, let alone development work!
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Thanks all for the great advice!!
I had planned the current limiting but have not got round to using it yet. I was planling to use the ACS hall effect ICs however in a compact board I'm thinking that the magnetic fields through the traces might lower the accuracy. I was planning to use just 1 sensor on the negative wire leading to the battery just for current limiting purposes.
I have seen the Vedder Board and that thing is a work of art and is something I am aiming towards.
Do I add snubber footprints for both the low and high side mosfets just in case?
So here is how I will proceed.
1. I will add 100nf MLCC acros + and - of each half bridge, maybe that will help a bit just to make things safer for when I am running the motor.
2. I will run the motor at low voltage to begin with (say 12V) and monitor the voltages. (Do I need to monitor for example across one high side mosfet Vds or do I monitor between mosfet pahses?)
3. I will add current sensing and limitng.
4. Implement SPWM using hall sensors only using angle estimation (should be fun).
5. Conslidate the PCB design with a proper layout!
I guess I can compare the voltages of the two layouts and it should give me a good comparison.
I will keep you posted.
First order of businesses Implementing the BLDC code again and re testing it
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Just for my understanding:
I see no commutation circuitry, neither Hall-sensor nor back-EMF sense. Perhaps it's on a different part of the schematic.
Or is this in reality a PMSM design?
This question does have consequences for the driver stage.
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Just for my understanding:
I see no commutation circuitry, neither Hall-sensor nor back-EMF sense. Perhaps it's on a different part of the schematic.
Or is this in reality a PMSM design?
This question does have consequences for the driver stage.
The hall sensor circuitry is relatively simple, the hall sensors are connected to interrupt pins of the micro controller using internal pull-up resistors
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DC link input current measurement might not be quick enough, depending on the amount of capacitance directly on the bus. Of course you can place the shunt so that most of the bulk capacitance is before it.
Integrated desat is preferred since it comes automatically in many gate driver ICs and while not good enough for precise torque control, it's ok for crude current limit for protection.
I had good results using DRV8302 in my first ever BLDC motor design.
If you think about your bridge and how the motor is connected, having current sense in two of the phases, on bottom legs only (below the FET) is enough and will protect you from any faulty PWM state - of course as long as you move to a safe state when you detect the overcurrent (000, 111, ZZZ, etc.).
You get a quick start once you understand that when you map the 3 hall sensor wires (3-bit value) as an index to table[8], which gives you the rotor magnetic position directly (6 steps, 0 to 5) and use that position to index sine table at three different offsets (base, +120 and +240 degrees), and use these values as the PWM values - 50% duty is the zero point. And you have a simple and completely usable BLDC speed controller. Add a multiplier to tune the torque, and some current limit code to quickly turn down that multiplier - or, if severe overcurrent, just turn it off.
For the open collector hall sensors, that's a noisy environment, especially with a bad layout. MCU internal pullups are almost always too high in value (20-50k?). I used external 4.7k + 220R series + 1500pF ceramic cap for filtering in my first design.
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Yes, you want to minimize loop area to cut inductance. I have built some similar servo drives. I use the IR2113 half-bridge driver in some of them. Across the low side transistor, I have an ultra-fast diode to prevent the junction of the two transistors from going below ground when the top transistor shuts off, and the load inductance wants current to keep flowing out of the half bridge. Also, I use a 10 Ohm resistor and 10 nF cap in series as a snubber. Note that the resistor will run hot, so I use a several Watt non-inductive part.
The inductance causing the common point between the two transistors falling below ground will burn out my IR gate driver. Not sure that your part can handle that condition. Do NOT trust the "body diode" in the FET, they are completely awful. I measured forward turn-on taking several microseconds at up to 12 V! Certainly the slowest diode turn-on I've ever seen.
Jon
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Eliminate all the jumpers, they add inductance.
Layout is everything in power electronics. Gate driver design is deceivingly tricky so don't get too discouraged with your first design not behaving as you would expect.
Your layout needs to control the loop areas for gate drive signal and DC bus. Your DC bus should overlap to minimize loop area. High DC bus inductance will rear it's head as turn off overshoot on your drain to source pins. While your layout needs serious work, you should try slowing down your gate-source switch time by increasing your gate resistor. I typically target 800ns to start and work from there. Controllers under 1kW tend to be pretty forgiving of poor layout.
Be very careful where you ground your scope since you are not using differential probes as you can damage your scope and board. With normal probes the best way I've found to do power electronics work is to put the ground on the phase out and then invert the signal trace when making measurements on the low side. When making measurements you don't want to use the jumper lead as it adds inductance which can show up as ringing that really isn't there.
I've designed a 7.5kW (20kW peaks) 120V DC bus controller I've been playing with for some time on an ebike and various other projects. I've posted the schematic and Kicad layout files if you want to take a look. I used the TD350E gate drive and ran fully isolated power supplies to all the gate drives.
There is some good discussion in this thread. The one poster, Highhopes has done power electronics in the Aerospace world so pay attention to what he says. He's the guy that taught me.
https://endless-sphere.com/forums/viewtopic.php?f=30&t=58341&hilit=controller
Have fun, try not to make too many plasma balls!
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DC link input current measurement might not be quick enough, depending on the amount of capacitance directly on the bus. Of course you can place the shunt so that most of the bulk capacitance is before it.
Integrated desat is preferred since it comes automatically in many gate driver ICs and while not good enough for precise torque control, it's ok for crude current limit for protection.
I had good results using DRV8302 in my first ever BLDC motor design.
If you think about your bridge and how the motor is connected, having current sense in two of the phases, on bottom legs only (below the FET) is enough and will protect you from any faulty PWM state - of course as long as you move to a safe state when you detect the overcurrent (000, 111, ZZZ, etc.).
You get a quick start once you understand that when you map the 3 hall sensor wires (3-bit value) as an index to table[8], which gives you the rotor magnetic position directly (6 steps, 0 to 5) and use that position to index sine table at three different offsets (base, +120 and +240 degrees), and use these values as the PWM values - 50% duty is the zero point. And you have a simple and completely usable BLDC speed controller. Add a multiplier to tune the torque, and some current limit code to quickly turn down that multiplier - or, if severe overcurrent, just turn it off.
For the open collector hall sensors, that's a noisy environment, especially with a bad layout. MCU internal pullups are almost always too high in value (20-50k?). I used external 4.7k + 220R series + 1500pF ceramic cap for filtering in my first design.
I am using isolated discrete gate drivers (half bridge UC20520). I get what you are saying about the capacitance. Do you think instead of shunts that the ACS hall effect current sensors would work on a small layout board because of all the magnetic fields everywhere?
I have already implemented a 6 step commutation system with hall sensors in the past. For SPWM with hall sensors I found an Application note that states you need to measure the speed of the motor and angle so you can set the 'cycle ' (frequency) of the sine wave correct?
So you put a 4.7k pull up resistor and and Rc filter on the signal wire correct? I am assuming that this was put on the PCB of the controller and not on the PCB inside the motor because of the long wire leads.
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Yes, you want to minimize loop area to cut inductance. I have built some similar servo drives. I use the IR2113 half-bridge driver in some of them. Across the low side transistor, I have an ultra-fast diode to prevent the junction of the two transistors from going below ground when the top transistor shuts off, and the load inductance wants current to keep flowing out of the half bridge. Also, I use a 10 Ohm resistor and 10 nF cap in series as a snubber. Note that the resistor will run hot, so I use a several Watt non-inductive part.
The inductance causing the common point between the two transistors falling below ground will burn out my IR gate driver. Not sure that your part can handle that condition. Do NOT trust the "body diode" in the FET, they are completely awful. I measured forward turn-on taking several microseconds at up to 12 V! Certainly the slowest diode turn-on I've ever seen.
Jon
That is good to keep in mind. I have used the IR2184 in th epast which is similar to the 2113. For this I am using the UCC20520 by TI as it has isolation on board.
I keep the body diode in mind ;) I'll run minimal tests on this and I'll completely redesign it. have a bit of information overload with all the good tips on this thread so I have plenty of work to do!
Thanks so much, gotta learn quick
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Eliminate all the jumpers, they add inductance.
Layout is everything in power electronics. Gate driver design is deceivingly tricky so don't get too discouraged with your first design not behaving as you would expect.
Your layout needs to control the loop areas for gate drive signal and DC bus. Your DC bus should overlap to minimize loop area. High DC bus inductance will rear it's head as turn off overshoot on your drain to source pins. While your layout needs serious work, you should try slowing down your gate-source switch time by increasing your gate resistor. I typically target 800ns to start and work from there. Controllers under 1kW tend to be pretty forgiving of poor layout.
Be very careful where you ground your scope since you are not using differential probes as you can damage your scope and board. With normal probes the best way I've found to do power electronics work is to put the ground on the phase out and then invert the signal trace when making measurements on the low side. When making measurements you don't want to use the jumper lead as it adds inductance which can show up as ringing that really isn't there.
I've designed a 7.5kW (20kW peaks) 120V DC bus controller I've been playing with for some time on an ebike and various other projects. I've posted the schematic and Kicad layout files if you want to take a look. I used the TD350E gate drive and ran fully isolated power supplies to all the gate drives.
There is some good discussion in this thread. The one poster, Highhopes has done power electronics in the Aerospace world so pay attention to what he says. He's the guy that taught me.
https://endless-sphere.com/forums/viewtopic.php?f=30&t=58341&hilit=controller
Have fun, try not to make too many plasma balls!
Thanks!
I have a 10ohm gate resistor and measured a rise time of around 200ns. Wouldn't increasing the gate resistor increase the rise time and drastically increase the switching losses. I am running a switching freq of 32 khz but am thinking of winding it down to 25kHz (I just hate the switching sound at low freqs)
Thanks for the info about the jumpers, how do you recommend I take measurements on parts without these jumpers to avoid this problem?
I am also using full isolation. I am running the UCC20520 it is fully isolated. U sing a 15V to 5V isolated DC to DC for my isolation.
I'll take a look at your thread in detail and use it for inspiration.
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I also suggest reading through this PDF as it covers some really good info on designing a gate drives, but unfortunately does not cover component layout.
http://www.ti.com/lit/ml/slua618/slua618.pdf (http://www.ti.com/lit/ml/slua618/slua618.pdf)
Layout is absolutely critical on a gate drive. Even something as minute as orienting capacitors in one direction vs another can matter due to inductance.
I don't see any ground planes on your board beneath the gate drive traces, this is pretty much mandatory, but must be done correctly. The way you attach ground planes to the power devices can matter as well depending on power level. The gate/source connections (drain too if using a drive with a desaturation feature) are typically made similar to a kelvin type connection used to measure resistance to help minimize noise intrusion onto the ground plane.
I want to point out a safety issue (not much of an issue on your low power design) that you'll hopefully read up on more. You are running traces underneath the gate drivers which reduces the isolation on your devices. You NEVER run anything under a device which provides electrical isolation. Often times you'll see slots cut in the PCB to aid in isolation. What you should see on your board if you hold it up to the light is opaque spots where your power pass section, translucent spots where your isolation barrier is.
To answer your questions:
A higher value gate resistor will increase the rise/fall time. Your ringing is really bad. Slow your switching time down to 800ns and see how that changes the ringing and overshoot. General rule of thums is you only switch as fast as you need to. If I'm reading it correctly your +20V overshooting after turn off on a 48V DC bus. No good. Ringing = making noise= the enemy. You should not need any snubbers for this project other than something like a 1-5uF polypropylene cap on your bus as close to the switching devices as possible. Your DC link caps should not have any leads showing due to inductance. Best type of cap for DC link is polypropylene, but enough electrolytics will get the job done if you don't care about cap life or have low ripple current.
To make measurements, use a probe holder of some sort and this type of lead if possible https://i.stack.imgur.com/7OPgl.jpg (https://i.stack.imgur.com/7OPgl.jpg) Make your own ground leads like this out of solid copper wire and solder them in the place you want to measure. Short leads is the key. If you have access to differential probes, use those, they make life so much easier.
You should consider also use 2 different bypass capacitor values 10/100nF on the gate drive power pins as close as possible to the driver chip. A larger 10uF ceramic cap would also help with instantaneous current demand.
If you want to really learn this stuff, study Maxwell's equations and think about the physics at play.
This video does a good job illustrating the physics.
https://www.youtube.com/watch?v=9Tm2c6NJH4Y (https://www.youtube.com/watch?v=9Tm2c6NJH4Y)
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Hi all
First of I'd like to say a big thanks to all of you that replied I learned a lot from this tiny thread and will be looking to make these improvements.
Firstly however I am testing the effect of the electrolytic bootstrap capacitor in parallel with the ceramic bootstrap capacitor and tomorrow the 'turn of gate resistor diode'
I have taken measurements using the scope my RIGOL DS1054z and the results are pretty evident as seen below. (I took the measurements with the regular probes and I know these may not be ideal but they will do for this testing phase)
The only problem seems to be that the sampling rate on my scope is too low. I tried increasing the memory depth but all it does is add more cycles. Is there anyway to fix it? If I use the averaging sampling technique I think that might ruin my render measurements null?
(https://i.imgur.com/6xhbANN.png)
Like this maybe it doesn't look so bad!
(https://i.imgur.com/WQwwaRr.png)
Do you think this is good enough to presnet in a thesis if I add the average sampling function to counter act that I am probing from the headers which add inductance? ;)
Thanks!
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You may be aware of it already, but this blog:
http://scolton.blogspot.co.uk/p/motor-controllers.html (http://scolton.blogspot.co.uk/p/motor-controllers.html)
by Shane Colton covers a wealth of "DIY" motor controller design and experimentation!
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I also suggest reading through this PDF as it covers some really good info on designing a gate drives, but unfortunately does not cover component layout.
http://www.ti.com/lit/ml/slua618/slua618.pdf (http://www.ti.com/lit/ml/slua618/slua618.pdf)
Layout is absolutely critical on a gate drive. Even something as minute as orienting capacitors in one direction vs another can matter due to inductance.
I don't see any ground planes on your board beneath the gate drive traces, this is pretty much mandatory, but must be done correctly. The way you attach ground planes to the power devices can matter as well depending on power level. The gate/source connections (drain too if using a drive with a desaturation feature) are typically made similar to a kelvin type connection used to measure resistance to help minimize noise intrusion onto the ground plane.
I want to point out a safety issue (not much of an issue on your low power design) that you'll hopefully read up on more. You are running traces underneath the gate drivers which reduces the isolation on your devices. You NEVER run anything under a device which provides electrical isolation. Often times you'll see slots cut in the PCB to aid in isolation. What you should see on your board if you hold it up to the light is opaque spots where your power pass section, translucent spots where your isolation barrier is.
To answer your questions:
A higher value gate resistor will increase the rise/fall time. Your ringing is really bad. Slow your switching time down to 800ns and see how that changes the ringing and overshoot. General rule of thums is you only switch as fast as you need to. If I'm reading it correctly your +20V overshooting after turn off on a 48V DC bus. No good. Ringing = making noise= the enemy. You should not need any snubbers for this project other than something like a 1-5uF polypropylene cap on your bus as close to the switching devices as possible. Your DC link caps should not have any leads showing due to inductance. Best type of cap for DC link is polypropylene, but enough electrolytics will get the job done if you don't care about cap life or have low ripple current.
To make measurements, use a probe holder of some sort and this type of lead if possible https://i.stack.imgur.com/7OPgl.jpg (https://i.stack.imgur.com/7OPgl.jpg) Make your own ground leads like this out of solid copper wire and solder them in the place you want to measure. Short leads is the key. If you have access to differential probes, use those, they make life so much easier.
You should consider also use 2 different bypass capacitor values 10/100nF on the gate drive power pins as close as possible to the driver chip. A larger 10uF ceramic cap would also help with instantaneous current demand.
If you want to really learn this stuff, study Maxwell's equations and think about the physics at play.
This video does a good job illustrating the physics.
https://www.youtube.com/watch?v=9Tm2c6NJH4Y (https://www.youtube.com/watch?v=9Tm2c6NJH4Y)
Thanks for your help.
I have watched the video and it does put help put thing into perspective, I will make sure to not run traces between ICs with Isolation on my final version. A 4 layer board should help with that.
I have differential probes at my uni and I will use them to take my final measurements.
You want to use different sized bypass capacitors to help with the frequency response as different sized caps will have a different impedance that will vary with the frequency you are running right?
With regards to current sensing are hall effect sensors such as the ACS712 and similar good for this application as a dense board layout might introduce more noise into the system. I want to use these since they have isolation built in and with a regular shut Id have to get an isolated op amp otherwise I'd lose my isolation.
Thanks!
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You may be aware of it already, but this blog:
http://scolton.blogspot.co.uk/p/motor-controllers.html (http://scolton.blogspot.co.uk/p/motor-controllers.html)
by Shane Colton covers a wealth of "DIY" motor controller design and experimentation!
Oh my!,
That is a gold mine and I was not aware of that. I will start reading up on his thesis as it seems like a great source to learn from.
I have seen those mosfet modules before such as the MTI 85W100GC. Should I go for one of them in the final board for compact design or should I go for discrete Mosfets. Also they do come with that copper plate on the bottom correct for heatsinking as it is not clear in the datasheet!
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Update:
So when I looked at my set up all of the stuff you guys said about inductance came into my mind and I was horrified! So I cleaned up some of my connections and saw an immediate improvement to my load spike voltage. It dropped form 70V to less than 60V. It could be down to the fact of improved load connections or improved probe connections.
I also added a 100nF ceramic capacitor across each half bridge and it made a huge difference.
(https://i.imgur.com/YtiJsis.jpg)
Here are the difference the capacitor made:
(https://i.imgur.com/3wLmvmW.png)
The previous voltage spike was almost 60V and now the voltage spike is barely over 48V! So that is a huge improvment!!
I also got the results below. I was testing what effect the turn off diode in parallel with the gate resistor would have. I do not know really how to interpret these results. Across Vgs of the High side FET the diode actually makes things worse as it introduces quite a bad negative voltage transient. Across the resistive load, there is no noticeable difference. This leads me to think I could do without this diode as it makes things worse across Vgs and has no effect on the load and it would save space and cost at the PCB. I do not think it should effect an inductive load, since there is no difference in the resitive load. Is this a good assumption?
(https://i.imgur.com/S81k3E9.png)
(https://i.imgur.com/BtunFIC.png)
Any thoughts?
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Any thoughts?
You understood the issue, learned quickly, processed that information and found out how to improve it, and actually measured your success in no time. I'm sure you'll be a great power electronics designer sooner than many would expect seeing the first layout. :-+
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Lots of excellent advice have already be given to you Glenn. I think you need to put things into perspective, as many aspects depend on the power level and maximum current your system is supposed to deal with.
Past some power point, you shouldn't need to use snubbers. I can't draw a line, but I haven't see any snubbers in typical "mobility" motor controllers of some 200W and up. Snubbers in this application/power level are a kind of a bandaid.
You should check for ringing at your system's maximum current, as ringing amplitude is very strongly current dependent. Then let us know if your snubber capacitor isn't warming up. Search for "double pulse test".
The diode in parallel with the gate resistor will make the switch off very fast, and faster = higher amplitude transients; dv = L di/dt is your law in this application, as has already been mentioned by previous posters. That technique is used to control turn on and turn off times separately, but a resistor is inserted in series with the diode.
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And by the way... a motor is quite a different load than a resistor. You should use a motor, or at least an equivalent coil, in your tests. I do mine on a motor with a locked rotor.
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Implement the pulse-by-pulse (or at least as quick as possible) current limit, test it works with your resistor load, then switch to the actual motor as soon as possible. Start with lower DC link voltage first.
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Thanks all for the advice!
I am aiming for around 1kW so 48V and roughly 20A.
What I will do next As @nuno and @Siwastaja recommended is,
1: Test with the voltage on the load with 2 motor wingdings as the load. I will go to uni to use a current limited supply. I will start at 20V since I need that cause of the 15V buck converter. I will then run at 32V. I will also increase the current limits at each stage to see what effect that has since as you said is VL = L.di,dt.
2: Then I will retest the hall sensor sequence with reference to hte pahses so that I can re implement my old code.
PS some people measured to motor's inductance and it is apparently 311uH at 400Hz
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The double pulse test is a switching test in a controlled fashion. You can even just charge your bulk capacitors to your test target voltage and disconnect the power supply for added "safety". Here's one I did on a 25V 20A H-bridge and posted in another topic:
(https://www.eevblog.com/forum/projects/small-ev-speed-controller/?action=dlattach;attach=108190)
This captures the end of the 1st pulse and the start of the second.
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The double pulse test is a switching test in a controlled fashion. You can even just charge your bulk capacitors to your test target voltage and disconnect the power supply for added "safety". Here's one I did on a 25V 20A H-bridge and posted in another topic:
(https://www.eevblog.com/forum/projects/small-ev-speed-controller/?action=dlattach;attach=108190)
This captures the end of the 1st pulse and the start of the second.
I have looked up up the double pulse and found some really good info so thanks for that! From what I read, the second pulse produces a larger voltage spike since the inductor already has stored current. Do you have pictures of the second pulse? To be honest I was thinking of running this test on my final compact version of this pcb as I am going to make another one to fx all these mistakes.
If I can pick your brain. what do you think about this type of MOSFET module? http://ixapps.ixys.com/Datasheet/MTI85W100GC.pdf (http://ixapps.ixys.com/Datasheet/MTI85W100GC.pdf) the MTI85W100GC as compared to discrete mosfets?
I would think this would have less inductance, small size and possibly better heat transfer, however you cant replace one FET if it is burnt out.
It look somthing like this as seen in Shane colton's blog.
(https://i.imgur.com/XpplDJQ.jpg)
And do all of them come with the copper thermal pad on them as I cannot find any specific reference to it in the data sheet
Regards!
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Any thoughts?
You understood the issue, learned quickly, processed that information and found out how to improve it, and actually measured your success in no time. I'm sure you'll be a great power electronics designer sooner than many would expect seeing the first layout. :-+
Thanks so much for your kind words, looking forward to improve
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I have looked up up the double pulse and found some really good info so thanks for that! From what I read, the second pulse produces a larger voltage spike since the inductor already has stored current. Do you have pictures of the second pulse?
I don't, but it's not necessary, because, as you said, by the end of the 1st pulse the current is already around the value you want to test at, and the small time it takes from the end of the 1st to the start of the 2nd doesn't allow the current to drop significantly, so both (raise and fall) edges are caught on this graph. I captured these 2 instead of the 2 from the 2nd pulse just for convenience.
To be honest I was thinking of running this test on my final compact version of this pcb as I am going to make another one to fx all these mistakes.
I think you should do it on the layout you currently have (and with the same scales) because it will be a valuable experience and you'll be able to do a direct comparison later with you improved layout(s).
If I can pick your brain. what do you think about this type of MOSFET module? http://ixapps.ixys.com/Datasheet/MTI85W100GC.pdf (http://ixapps.ixys.com/Datasheet/MTI85W100GC.pdf) the MTI85W100GC as compared to discrete mosfets?
I would think this would have less inductance, small size and possibly better heat transfer, however you cant replace one FET if it is burnt out.
I don't really have much experience in this area, but from what I see, the advantages a module has is mainly in compactness, design ease and yes, less inductance (especially on the motor/phase exit node, responsible for the turn-off transient). On the other hand, they tend to be (sometimes much) more expensive than using equivalent discreet FETs. There's also much less options.
By the way, the h-bridge from the double pulse test I posted has a relatively bad layout, but since it has a significant parasitic inductance in the GND connection from the driver to the FET, it provides negative feedback putting a brake on di/dt.
In the graph you can also see the top/bottom FET switching deadtime; the phase current re-circulating on the top FET body diode causes the slight voltage raise (1 diode drop) that can be seen right after switch off and right before switch on. In the central part of the graph Vds is slightly lower because current is re-circulating through the top FET turned ON (looks like I could improve by halving the top-to-bottom-switch deadtime).
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Yeah that definitely is a good idea to compare so Im going to do it. I am however first going to finalize my code to test that the motor rotates before just incase.
So a couple questions. did you do it with a locked rotor test? If so you did have to somehow limit the current that goes in cause with a locked rotor the currents must be massive!
I am going to follow this: http://athenaenergycorp.com/wp-content/uploads/2016/03/Rogowski_double-pulse_testing.pdf (http://athenaenergycorp.com/wp-content/uploads/2016/03/Rogowski_double-pulse_testing.pdf)
However I am surprised that in this resource apparently as seen in the graphs provided the switch voltage does not overshoot.
Do you have to repeat the test in the other direction, ie probing the top side mosfet ot can you assume similar values?
With regards to the FET module it is a bit more expensive, the mosfets I have currently would cost around 13 euros for 6 of them while the module costs around 20 euros. So I am a bit conflicted it is however a very convenient package I emailed them for some more info regarding the thermal pad and I will see
Thanks!
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So a couple questions. did you do it with a locked rotor test? If so you did have to somehow limit the current that goes in cause with a locked rotor the currents must be massive!
The current for the double pulse test I controlled by adjusting the ON time of the 1st pulse until it gets to the current I want to test at. In this controller I measure current with a 5mOhm shunt. Nevertheless, as Siwastaja has already mentioned, you really should (not to say must*) control the current (PWM) pulse-by-pulse. I have a voltage comparator comparing the voltage drop on the shunt with a constant value (set by a trimpot, but could be a DAC or something else), and its output is connected to an interrupt pin on the microcontroller. When the "overcurrent" interrupt triggers, the ON time of the PWM is terminated, regardless of currently set duty cycle. As simple as this.
For several reasons, you'll never be able to limit the motor/phase current by setting a limit on your power supply.
I am going to follow this: http://athenaenergycorp.com/wp-content/uploads/2016/03/Rogowski_double-pulse_testing.pdf (http://athenaenergycorp.com/wp-content/uploads/2016/03/Rogowski_double-pulse_testing.pdf)
However I am surprised that in this resource apparently as seen in the graphs provided the switch voltage does not overshoot.
It's just a concept diagram, not a real world scopeshot ;)
Do you have to repeat the test in the other direction, ie probing the top side mosfet ot can you assume similar values?
I think if you have a symmetrical layout it should be similar, but to be sure, I think you should measure.
* Well... it actually depends on the application.
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Perfect!
So due to the limitations on my layout (I did not include a current sensor), what I will have to do is to remove the big electrolytic caps, and add the current sensor on the negative DC link to get more accurate-ish measurments. I have a current sensor on the way/ Its the ACS711 is a hall effect. I will use that to keep the isolation between my power and signal circuits because with the shunts I lose my isolation unless I add a bunch other stuff!
The ACS711 has a fault pin aswell so that is usefull
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You can't remove the DC link caps, unless you want to have a huge voltage spike in the DC bus at FET turn off. Why do you want to remove the caps?
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I was going to remove the because I can only add the current sensor between the battery and the PCB due to the layout. And if I tridgger the double pulse at 20A, it wouldn't really be really 20A since the caps are also supplying current or is the difference negligible? Each cap is rated at around 2.5 A ripple current and I have 2 in parallel.
I was going to remove them and solder them in between the battery lead wires before the current sensor to get a more accurate measurement.
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The caps should be as close to the FETs as possible.
What matters here is the motor/phase current, and it's where you want to test the 20A. You're right that the caps will supply part of it, and it's just the way it works, because the power supply won't be able to give 20A fast enough due to parasitic inductance (wiring, etc). Actually, you can have 20A at the motor and, say, 4A at the battery side; a motor controller is kind of a buck switching regulator without the output cap. So you can put your current sensor on the motor wiring.
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Sensing the current in motor phases is the right way to go for two reasons:
1) You get reading of all three phases separately (with two measurements), instead of total current only
2) The DC link caps don't smooth the reading out, so you get quicker response
But, DC link measurement is much better than nothing, and certainly doable.
Now, if you want to have a protection against motor inductor starting to saturate, and current starting to rise more quickly than you expect, you need to have the shunt placed so that there is no enormous amount of capacitance which would supply the motor, delaying the current rise in the shunt. Small amount is of course OK, since it's "used up" while switching, i.e., in microsecond timescale. And, it has to be that way, because you need it physically close to the FETs, no space to add the common measurement shunt there.
Large amounts of bulk capacitors can actually slow down your current measurement too much to react safely in time, so in that case, you'd place the shunt between the DC link (sprayed with small low-ESL caps and maybe some part of the bulk capacitance), and the rest of the bulk capacitance.
As you know the motor winding inductance and the supply voltage, you can calculate the rate (A/µs) the current rises when you apply full input voltage over the motor phases. V = Ldi/dt -> solve for di/dt. And, if you know the nominal "maximum phase current" for motor it's supposed to run at (rather continuously), and assume that it starts to severely saturate at 3x that current, then you can easily calculate how long it takes for the current to reach that value if your PWM is stuck at the wrong state, i.e., how fast do you need to react to the current measurement getting over your limit.
Then, the same for capacitance is: i = Cdv/dt -> solve for dv/dt to see how quickly the capacitor voltage fades when you supply the current I from the caps.
You can get a lot fancier with maths and all that, but this should give you an idea what's this all about. Actually modeling this would require you to model the input wire inductance and resistance - how quickly it replenishes those DC bus caps while you are measuring.
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So from your feedback what im going to do is run the test with current sensors on the motor phase. on both systems to compare them! I am getting some free samples current sensors. I am going to use the ACS733 which is a hall effect current sensor, I can program the current limit for it and if it is exceeded it gives me a fault which can go to external interrupts on the micro controller.
Speaking of which I ran in a bit of a snag while programming the code for the hall sensors. I programmed that the hall sensors would be connected to eternal interrupts on the uC. This can be set to level triggered (which is not good for this application), or edge triggered. Then you have to set if it is rising or falling edge. Therefore between some transitions the interrupt would not realize that the hall sensors have changed state. Because if you set for example one sensor to be falling edge triggered, when it would rise, nothing would happen. I made a truth table to see if there are any combinations which would work but there aren't any.
Therefore what I have to do is use capture inputs of the time which work by detecting a state change. Although this will take a rework and learning since I never used them, it has the added bonus of counting the time between the state change, therefore I can detect the motor speed and use that for SPWM which makes life easier in the long run.
So before I run the hardware test I need to figure out the software First
Cheers!
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I just decode the three-bit hall input to a 6-step value in the (only) control ISR (that does everything else as well) running at around 50 kHz IIRC. Works very well, and is extremely simple. But if you run at extremely high fundamental frequencies, this method doesn't give the exactness of reacting to the state changes through timer input captures when they happen.
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I just decode the three-bit hall input to a 6-step value in the (only) control ISR (that does everything else as well) running at around 50 kHz IIRC. Works very well, and is extremely simple. But if you run at extremely high fundamental frequencies, this method doesn't give the exactness of reacting to the state changes through timer input captures when they happen.
I get what you mean, In my first version using an arduino I used to ask the uC continuously to check the digital pins and at higher speeds the motor would start cogging a bit because it was not fast enough. I'm guessing you had a similar problem.
I have now switched to an ARM7 uC granted not as fast as the new CORTEX but still will do the job. What type of interrupt where you running? Just a normal timer interrupt at 50kHz? Because using a capture input should give me an interrupt every pulse and I should not miss any like this. Gotta catch'em all :-DD
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No, I have no problem whatsoever with code performance. I'm running the control loops in the ISR, triggered from the PWM generation timer, which is a logical place to do it, since it's nicely synchronized with the PWM generation (i.e., calculate the new PWM setpoints once for each new cycle) and ADC reading (i.e., one new current reading per PWM cycle is processed right here, right after conversion), and it's fast enough to also read the halls, so why not.
Running on ARM Cortex-M0 at 48MHz so not that much processing power, but not too much bloat, so definitely about two orders of magnitude faster than an Arduino.
Although, I could imagine some special cases where I would like to have more resolution to when the hall sensors actually changed state between the ISRs, for that I'd use input capture.
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Are you running 6 step commutation or SPWM? What you did with the PWM interrupt is a good effective solution for that
So I implemented the capture input for the hall sensors and it was relatively pain free. Today I tested the motor out on a current limited supply at uni and it worked great using 6 step commutation using my LPC2119. Then I tested it using a battery and it worked great so that's I guess is the first milestone.
Though I have a broad idea on how to implement SPWM, I am going to do some research today to find the best way to implement it. So that is the next goal. Then all that remains is to implement PID for a DC link current limit and I can start designing the final version of the PCB!
Thanks
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SPWM can mean anything based on who you ask, but I basically modulate the PWM value based on a sine lookup table. This is because even though I'm now just skipping the values through in 6 steps, I originally planned to interpolate inbetween and will do it soon... (I had the sine interpolation in place first, it works very well at modest and high speeds, extremely smooth and quiet running; but in it's most simple form, it was problematic when running extremely slowly (think about 1Hz), so I just removed it.)
Right now, I simply do it in 6 steps based on the current hall position, so the field direction wiggles around 60 and 120 degrees instead of the "optimum" 90 degrees. This keeps the motor running automatically, and the applied amplitude basically configures the current and hence torque (and that way, acceleration). So I have a PID loop around the speed, outputting the amplitude. Speed is measured by the time between the hall state changes.
Works so well that I haven't revised my code for a long time, just running it in the application doing gazillion of other things, but now I happen to need sub-hall-step-precision positioning so need to revise it soon...
Sorry, this code doesn't look very nice, was done in hurry. I stripped down some unimportant details, but just to give the idea what performs well even though very simple.
const int hall_loc[8] =
{
-1, // 000 ERROR
1, // 001
3, // 010
2, // 011
5, // 100
0, // 101 Middle hall active - we'll call this zero position
4, // 110
-1 // 111 ERROR
};
#define PH120SHIFT (1431655765UL) // 120 deg shift between the phases in the 32-bit range.
#define PH90SHIFT (1073741824UL) // 90 deg shift between the phases in the 32-bit range.
#define PH45SHIFT (PH90SHIFT/2)
const int base_hall_aims[6] =
{
0,
PH120SHIFT/2,
PH120SHIFT,
PH120SHIFT+PH120SHIFT/2,
PH120SHIFT*2,
PH120SHIFT*2+PH120SHIFT/2
};
#define HALL_ABC() ((GPIOB->IDR & (0b111<<6))>>6)
#define HALL_LOC() (hall_loc[HALL_ABC()])
/*
The sine table is indexed with 8 MSBs of uint32; this way, a huge resolution is implemented for the frequency,
since the frequency is a term added to the indexing each round. <-- this comment was written when interpolating between hall updates :)
*/
const int sine[256] =
{
0,804,1607,2410,3211,4011,4807,5601,6392,7179,7961,8739,9511,10278,11038,11792,
12539,13278,14009,14732,15446,16150,16845,17530,18204,18867,19519,20159,20787,21402,22004,22594,
23169,23731,24278,24811,25329,25831,26318,26789,27244,27683,28105,28510,28897,29268,29621,29955,
30272,30571,30851,31113,31356,31580,31785,31970,32137,32284,32412,32520,32609,32678,32727,32757,
32767,32757,32727,32678,32609,32520,32412,32284,32137,31970,31785,31580,31356,31113,30851,30571,
30272,29955,29621,29268,28897,28510,28105,27683,27244,26789,26318,25831,25329,24811,24278,23731,
23169,22594,22004,21402,20787,20159,19519,18867,18204,17530,16845,16150,15446,14732,14009,13278,
12539,11792,11038,10278,9511,8739,7961,7179,6392,5601,4807,4011,3211,2410,1607,804,
0,-804,-1607,-2410,-3211,-4011,-4807,-5601,-6392,-7179,-7961,-8739,-9511,-10278,-11038,-11792,
-12539,-13278,-14009,-14732,-15446,-16150,-16845,-17530,-18204,-18867,-19519,-20159,-20787,-21402,-22004,-22594,
-23169,-23731,-24278,-24811,-25329,-25831,-26318,-26789,-27244,-27683,-28105,-28510,-28897,-29268,-29621,-29955,
-30272,-30571,-30851,-31113,-31356,-31580,-31785,-31970,-32137,-32284,-32412,-32520,-32609,-32678,-32727,-32757,
-32767,-32757,-32727,-32678,-32609,-32520,-32412,-32284,-32137,-31970,-31785,-31580,-31356,-31113,-30851,-30571,
-30272,-29955,-29621,-29268,-28897,-28510,-28105,-27683,-27244,-26789,-26318,-25831,-25329,-24811,-24278,-23731,
-23169,-22594,-22004,-21402,-20787,-20159,-19519,-18867,-18204,-17530,-16845,-16150,-15446,-14732,-14009,-13278,
-12539,-11792,-11038,-10278,-9511,-8739,-7961,-7179,-6392,-5601,-4807,-4011,-3211,-2410,-1607,-804
};
#define PID_I_MAX 2000000000LL
#define PID_I_MIN -PID_I_MAX
#define MIN_MULT_OFFSET 10
void tim1_inthandler()
{
static int mult = 0;
static int currlim_mult = 255;
static int32_t cnt = 0;
static int expected_next_hall_pos;
static int cnt_at_prev_hall_valid = 0;
static int cnt_at_prev_hall;
static int prev_hall_pos;
static int prev_ferr = 0;
static int f = 0;
static int pid_f_set;
static int64_t pid_integral = 0;
TIM1->SR = 0; // Clear interrupt flags
int hall_pos = hall_loc[HALL_ABC()];
if(hall_pos == -1) hall_pos = prev_hall_pos; // glitchy value -> assume previous
int reverse = (pid_f_set<0)?1:0;
if(hall_pos == expected_next_hall_pos)
{
// We have advanced one step in the right dirction
// calculate the frequency from the delta time.
if(cnt_at_prev_hall_valid)
{
f = (PH120SHIFT) / ((cnt-cnt_at_prev_hall));
}
else
{
f = 0;
}
cnt_at_prev_hall_valid = 1;
cnt_at_prev_hall = cnt;
}
else // We are lost
{
lost_count++;
cnt_at_prev_hall_valid = 0;
f = 0;
}
prev_hall_pos = hall_pos;
expected_next_hall_pos = hall_pos;
if(!reverse) { expected_next_hall_pos++; if(expected_next_hall_pos > 5) expected_next_hall_pos = 0; }
else { expected_next_hall_pos--; if(expected_next_hall_pos < 0) expected_next_hall_pos = 5; }
// Ramp the speed setpoint.
int next_pid_f_set = (spi_rx_data.speed*100);
if(next_pid_f_set > pid_f_set) pid_f_set+=256;
else if(next_pid_f_set < pid_f_set) pid_f_set-=256;
if((next_pid_f_set - pid_f_set) > -256 && (next_pid_f_set - pid_f_set) < 256) next_pid_f_set = pid_f_set;
// Run speed PID
int pid_f_meas = f>>3;
if(reverse) pid_f_meas *= -1;
int ferr = pid_f_set - pid_f_meas;
spi_tx_data.speed = pid_f_meas>>8;
if(!(cnt & 15)) // don't run the PID every round
{
int dferr = (ferr - prev_ferr);
prev_ferr = ferr;
pid_integral += ferr;
if(pid_integral > (PID_I_MAX)) pid_integral = PID_I_MAX;
else if(pid_integral < (PID_I_MIN)) pid_integral = PID_I_MIN;
mult = ((30*(int64_t)pid_f_set)>>10) /* feedforward */
+ ((50*(int64_t)ferr)>>12) /* P */
+ ((50*(int64_t)pid_integral)>>19) /* I */
+ ((50*(int64_t)dferr)>>12); /*D*/
}
// Generate the sine
// Hall magic: get the magnetic position of the rotor right now.
int loc = (base_hall_aims[hall_pos] + timing_shift + (reverse?(-PH90SHIFT):(PH90SHIFT)));
// Indexes to the sine table (arithmetic wrap-around utilized):
int idxa = (((uint32_t)loc)&0xff000000)>>24;
int idxb = (((uint32_t)loc+PH120SHIFT)&0xff000000)>>24;
int idxc = (((uint32_t)loc+2*PH120SHIFT)&0xff000000)>>24;
const int max_mult = 150*256;
const int min_mult = -150*256;
if(mult > max_mult) mult = max_mult;
if(mult < min_mult) mult = min_mult;
int sin_mult = mult>>8;
if(reverse) sin_mult *= -1;
if(sin_mult < 0) sin_mult = 0;
if(sin_mult != 0)
sin_mult += MIN_MULT_OFFSET;
// Calculate the final multiplier, which is the combination of the PID loop output and current limit
uint8_t m = (sin_mult * currlim_mult)>>8; // 254 max
TIM1->CCR1 = (PWM_MID) + ((m*sine[idxa])>>14); // 4 to 1019.
TIM1->CCR2 = (PWM_MID) + ((m*sine[idxb])>>14);
TIM1->CCR3 = (PWM_MID) + ((m*sine[idxc])>>14);
cnt++;
int current = latest_adc[1].cur_b-dccal_b; // Temporary solution only looking current in phase B, adc timing must be improved
spi_tx_data.current = current;
if(OVERCURR()) // DRV8302 configurable cycle-by-cycle current limit signal: the gate driver has already terminated the pulse, this is information about it.
{
LED_ON(); led_short = 0; // give long blink
currlim_mult-=50;
}
else if(current < neg_curr_lim || current > pos_curr_lim) // soft current limit (by shunt & amp & adc)
{
LED_ON(); led_short = 1; // give short blink
currlim_mult-=2;
}
else if(currlim_mult < 255)
currlim_mult++;
if(currlim_mult < 5) currlim_mult = 5;
}
-
Hey,
so I started doing my research on SPWM and I realize that I know much less that I thought. The more I read from different sources the more confused I become!
The following photos is how I tough SWPM was done but I'm pretty sure that it's wrong after doing my research. If you have some time to look for my reasoning in the photos.
(https://i.imgur.com/NLW7n3K.jpg)
(https://i.imgur.com/zriR0TK.jpg)
I thought that all SPWM was, that instead of switching the phases with a constant duty cycle, you vary the duty cycle from a look up table to get a sine looking wave form but I think this is wrong as seen below. Instead of getting a complete sine current as seen on the right if I do this method, I will get a smoothed version of the wave form on the left as seen in red, where there would be parts of it were the current would be 0 i.e. not sine.
(https://i.imgur.com/tfsooJn.png)
This is further confirmed byu this resource I found:
http://www.zilog.com/appnotes_download.php?FromPage=DirectLink&dn=AN0380&ft=Application%20Note&f=YUhSMGNEb3ZMM2QzZHk1NmFXeHZaeTVqYjIwdlpHOWpjeTloY0hCdWIzUmxjeTlCVGpBek9EQXVjR1Jt (http://www.zilog.com/appnotes_download.php?FromPage=DirectLink&dn=AN0380&ft=Application%20Note&f=YUhSMGNEb3ZMM2QzZHk1NmFXeHZaeTVqYjIwdlpHOWpjeTloY0hCdWIzUmxjeTlCVGpBek9EQXVjR1Jt)
As opposed to trapezodial or block commutation,
in which two of the three phases are energized for each commutation step, the sinusodial commutation requires all three pahses to be energized for each step
So I am pretty sure I do not have the right concept. I can not understand what is the right ways to switch on the three pahses right now. I will keep doing some more research and try to understand your code.
It surely could not be as simple as say: when you are switching for example, the yellow high side mosfet(half bridge 1), you switch on both blue(half bridge 2) and green (half bridge 3) low side mosfets. Also I am only applying PWM to the high side FETS while keeping the lowside fets either completely on or completely off. Is this possible for SPWM?
Do you know a good resource to help me in understanding this?
Regards Glenn
-
So after a bunch of research I think I figured it out!
First I will implement what I found to be refereed to modified SPWM. Which basically is a trapezoidal control (only switching two phases on at time). However instead of switching them on symmetrically(with the same PWM value), You vary the PWM value to represent a sine wave.
To do this, I must first measure the motor speed to determine the frequency of the electrical cycle and then go from there.
Once I have implemented modified SPWM I will move on to full SPWM. I found a freat resource which states the following and after some matlab simulation #s this was also confirmed.
Using three different pointers PWM pulse width data values corresponding to the three phase
waveform are accessed. These pointers are adjusted so as to point to pulse width values that are 120
0
degree
phase shift apart in time from other. The number of PWM pulses per cycle is equal to f c /f m . Where f c is carrier
frequency and f m is modulating signal frequency. This number must be divisible by three in order to obtain
synchronous three phase PWM waveforms. For example if f c = 3600Hz and f m = 50Hz then number of pulses per
cycle is equal to 72. This number is divisible by three 72/3 = 24. So while accessing the pulse width values first
pointer points to zeroth location, second pointer points to 24
th
location of array and at the same time third
pointer points to 48
th
location of array. The following steps illustrate the algorithm to obtain the three phase
PWM waveforms using microcontroller;
1) Access the three phase synchronous PWM pulse width data values from look up table using three different
pointers to look up table.
2) Send the desired PWM code pattern at port pins.
3) Set the timer value with lowest pulse width value first.
4) Start the timer and wait until timer flag set.
5) Send the next desired PWM code pattern at port pins.
6) Set the timer value with next higher pulse width value.
7) Start the timer and wait until timer flag set.
8) Send the next desired PWM code pattern at port pins.
9) Set the timer value with next higher pulse width value.
10) Start the timer and wait until timer flag set.
11) Increment pointer by one and loop back step 1.
So I think I have the jist of it. I am sure that it will not be so easy but I have a good jumping off point
-
Hey All
So I have been designing a compact version of my controller. I have taken as much advice as possible from you guys. I have finished my first draft so to speak. If anyone can spare some time can you guys take a quick look at the gerber files to spot anything obviously wrong?
I plan on reviewing it again before finalizing it since I have never designed a PCB of this complexity.
Any advice will be greatly appreciated.
The Gerber files should be attached here: https://www.dropbox.com/s/93tcssz6w1glc7w/UCC20520%20Driver%20P0.32%20-%20CADCAM.ZIP?dl=0 (https://www.dropbox.com/s/93tcssz6w1glc7w/UCC20520%20Driver%20P0.32%20-%20CADCAM.ZIP?dl=0)
Thanks
-
Here Is my finalized design! Just waiting for the parts to arrive so I can check the footprints before I order the PCBs its a 4 layer board!
Some of the 3D render items such as the capacitor and the buck converter are messed up since I made some alterations to the footprints however the fottprints are correct. The big silk screen next to the FETs is space for the big electrolytic caps. I will lay them flat against the board. I know some of you suggested that this would increase the lead length and hence the inductance, however I think this is the most space efficecnt way to place them. They are labelled C1 and C2
(https://i.imgur.com/wdALwqS.png)
(https://i.imgur.com/ytCgXmP.png)
(https://i.imgur.com/WX0O3kk.png)
-
So this thread seems pretty much dead but I'll keep posting anyways.
My PCBs arrived,
(https://i.imgur.com/fiL6ILD.jpg)
Had 2 tiny (stupid) mistakes which I am SUPER disappointed about. 1- I connected the anode of the LCD back-light to ground by mistake on the schematic, and I when I was moving some components around, I didn't realize that on of the buck converter CAPS moved. Now its right up against the regulator, luckily it will still fit but only just.
Went over the PCB a couple of times so I'm very disappointed in myself that I didn't spot these but luckily they are not major and I can work around them. Hopefully there are no more mistakes lurking about.
Will solder it up and see if it works. Fingers Crossed
-
:-+
-
So here is Prototype 2 (P2). She is working :)
It is a 4 layer board whose FET layout is inspired by Vedder. Got total isolation from the logic side to the power side. This includes isolated current sensing as I am using Hall effect current sensing. Was my first time soldering QFN packages so I did butcher the Micro but it works.
It works well. Now looking t moving forward and running some thermal tests on it. Also looking at comparing trace inductance with the first version seen in the posts above.
In the mean time I have been working on P3 which will be similar to P2. However P3 will have temperature sensing, and an integrated 3 Phase Full Bridge (MTI85W100GC). Also the P3 will feature REALLY short tracks between the Gate Drivers and fets, since they will go from the top of the board to the bottom. This is aimed at reducing the inductance and hence making the circuit more hardy.
Any suggested Improvements of the P2 for the P3 are welcome
(https://i.imgur.com/dzsmlyx.jpg)
-
I'd get rid of that single large electro cap and replace it by more lower value surface mount versions. They could be mounted closer to the power switches too, and better spread across the power / ground planes. As output inductance generally isn't an issue, you could allow more room for some snubbers ?
-
That could work, it would also make the controller smaller, and cheaper. I also have an I identical cap on the bottom side of the board aswell. What values would you go with and how many?
As output inductance generally isn't an issue, you could allow more room for some snubbers ?
In what way do you mean more snubbers? Across the DC link or across all the high side fets and.or low side fets?
-
You can do a double pulse test under the same conditions and that will show you the "layout quality" of the several versions. One interesting test on the current version would be to test as you have now and test with the caps soldered flush to the board (in the vertical position). Don't save too much in uF for the DC link, as you can have situations of resonance with the battery wiring.
The problem with snubbers at these power levels is that tend to be big and heat up, so I don't see them in consumer products.
-
That's definitely a test I want to do since it is used in industry.
TO be honest it scares me a little bit since I don't want to destroy my boards incase it causes some super high voltage spikes.
It would be very interesting especially comparing the P1 to the P2. The test as you said on the P2 will also be very interesting, since it could justify switching to SMT caps as max_torque suggested above.
Still worried I could destroy my gate driver/fets, however I guess it is worth the risk. I'll start on the P1 since it is the most likely to have the biggest spike hence I'd rather destroy that than the P2
-
Well, best way to keep it safe is not power it up, ever :D
The double pulse is a highly controlled test. Start with smaller current (smaller current rampup time), and smaller switching speeds (higher gate resistor) so you get a feel for the initial behavior.
-
Yup Might as well go for it ;)
As the inductive load, I shall use my one phase of the motor to the +48V rail, while I will use another phase connected between the two birdges. I will also hjave the motor with locked rotor correct?
I will then apply the double side to the low side bridge
-
BAD NEWS, I NEED SOME ADVICE.
So I today I went to do some testing. I charged my 48V battery fully and started running the motor at full speed no load. Ran fine for around 10 seconds and 'THUD' the rotor locked up and everything shut off. At that point I knew I KOd one or more gate drivers.
I Checked for shorts and sure enough there was a short between my 15V and GND rails, so that could be either the buck regulator (unlikely) or the gate drivers, my money is on gate drivers. Tomorrow I will go to uni and un-solder them to se how many I KOd.
So assuming that the gate drivers are KOd, I believe this was caused by the inductance of the traces from my gate driver to the fets. Even Vedder himself had problems dealing with his VESC 4 were some motor would destroy his drivers as seen here below
https://youtu.be/1iwN5LGGM80?t=70
So as seen below there is roughly 5cm between the driver and the fets, I didn't think was too much but apparently it is.
(https://i.imgur.com/kBtXjbU.png)
So to fix this issue what I need to do is ensure that traces between the driver and the fets are minuscule. Naturally in this version this is not possible. Hence to fix this version what I propose on doing is the following:
1 - Use 100 ohms gate resistors, which slows down the turn on/off times.
2 - Add a 10nf capacitor across the gate and source of each fet, this also slows down the transients.
I think this hould fix my issues. Funny thing is that on my very first working controller. I had the PCBs set up in modules (one for gate drive, one for power stage) I was sending the drive signals over jumper cables between the two boards. The only different thing I had in my layout was the 10nf capacitor, which I currently do not have and that controller worked fine even with the long jumper wires. So I think although I am not fixing the issue, I am fixing the symptom at the cost of some efficiency.
In my P3 this should not be an issue, since I placed the gate drivers really close. as seen below there is rougly 1.5 cm. IS this too much?
(https://i.imgur.com/MYsArHf.png)
-
So assuming that the gate drivers are KOd, I believe this was caused by the inductance of the traces from my gate driver to the fets.
How does extra inductance to the gate cause the driver to fail?
-
I don't see how the driver - gate inductance can cause failure, either. Inductance will slow down gate charging and discharging - there is, switching speed. Do you have any gate resistor? Did you do the double pulse test 1st, before running the motor and analyzed the switching behavior? Vgs and Vds scopeshots will tell you alot.
-
I believe this issue is caused because of undershoot at the VSSA pin of the UCC20520 and having inductance in the traces between the FET and the driver does not help.
I currently have a 10 ohm gate resistor. I did not do the double pulse test, I was just running the motor normally to test my current sensors since I need to implement them before doing the double pulse test. However a mistake on my part is not taking any waveforms like you said while running. So I will fix that in the future.
O have been reading up and I think its because of the under voltafe, I have found this application not which is quite useful. https://www.infineon.com/dgdl/an-978.pdf?fileId=5546d462533600a40153559f7cf21200 (https://www.infineon.com/dgdl/an-978.pdf?fileId=5546d462533600a40153559f7cf21200)
These are the main points I took from it which highlights how to mitigate the under voltage:
(https://i.imgur.com/3e3QzSA.png)
(https://i.imgur.com/8L3mis6.png)
(https://i.imgur.com/J47RUi9.png)
(https://i.imgur.com/0VVFikS.png)
(https://i.imgur.com/TTaAfpi.png)
This last image is from the UCC20520 Datasheet
To hopefully solve this problem, I will do the following:
1 - Increase Gate resistor to 100 ohm (Not sure about this)
2 - Increase the low side capacitor according to the 4th image. In my case, both of them are the same (0.47nf) hence I will increase the lows ide capacitor to 4.7nf
3 - Add a 10nF capacitor between Gate and source. To produce cleaner waveform as in image 5.
4 - Take measurements on the gate driver.
I think based on the AN these are good adjustments to make. I am not sure about increasing Rgate too much since with the addition of the capacitor between gate and source it may slow down the switching too much
What do you think?
-
Bingo I think we have a winner!
(https://i.imgur.com/495utkq.png)
Here is the maximum undervoltage it tollerates -0.3V. So I will replace the driver and measure the under voltage I'm getting.
Here Is a post on a different form where a guy experienced what seems to be the same issue:
https://electronics.stackexchange.com/questions/322615/isoltaed-gate-driver-consistent-failure
What he did to solve the issue was he increased his sinking resistor and added schottky diodes from source to gate, Considering I dont have a turn of diode or resistor, what are my options apart from bodging them?
I will update you guys with scope shots from the driver soon!
-
Ok. In that case, increase Rg to 100R (bullet 1) is what I would do to start. Then measure.
Beware how you measure... use the short GND clip and make sure there's no problem with connecting your scope GND to a non GND circuit node.
-
100ohm gate resistor is HUGE for a motor driver this size, and it's going to seriously compromise the efficiency. 10ohm is on the right ballpark.
Hugely excessive switching times can get the FET outside of its safe operating area, since these FETs are designed for switching, not linear, dissipative operation.
You can definitely try that, but I'd recommend trying to find the actual cause of the problem instead. I'd recommend you to run at half DC link voltage, probing all possible signals for over/undershoots. Then scale up.
-
So Here is an update.
I removed all of my gate drivers and to my surprise they are NOT the issue. With them out of circuit, I still had the short between 15V and GND. After some more digging around, I found out that it was due to my buck converter.
I am using the LM2576HVSX-ADJ. I Bought it from mouser, so it must be a genuine part right?
I am using it to drive 15V. The interesting thing is that once I removed the regulator it is shorted between Pin 2 (Output) and GND. It is not shorted between Pin 1 (Input) and GND. This leads me to believe that something went wrong on the 15V rail not the input.
So here is my schematic.
(https://i.imgur.com/Aew1CnV.png)
This is the recommended schematic by TI. The differences I have, are the diode the inductor and the output capacitance.
Diode - My diode is a Schottkey diode I think it is fine.
Inductor - I used a 100uH ias reccomened on the diagram. In figure 31 of the data sheet, it shows that for a 100uh inductor at roughly 50V, it can supply a max current of 1.75A. I do not suspect this to be an issue.
Capacitor - O the output, my capacitor is much smaller I am using a 220uF instad of the 1000uF (for the fixed) and 2000uF for the adjustable on one diagram and 1000uF on the other diagram. however I don't think this is the cause, I shouldn't be drawing large amounts of currents for this application, since I am only driving an mcu, lcd, and the fets. Or is such a large CAP required for stability?
(https://i.imgur.com/VA2vzoH.png)
(https://i.imgur.com/SqofNz9.png)
Another issue that I am suspecting is the layout that I have used. I placed the regulator and all other components on the bottom while placing the inductor at the top due to space issues. Could this be causing some kind of issue?
(https://i.imgur.com/9Ta10Wm.png)
Could there be some kind of ringing when I switch the FETS that is causing an issue?
This is a really surprising issue for me. I have those cheap Chinese version of this regulator which I could unsolder and test again however I'd like to see what is the underlying issue before I blow it up again.
-
So I tested the standalone Chinese buck converter board. I connected a load resistor of around 8.4 ohms at 15V buck setting, with a 100uH inductor. When I switched on the buck first and then connected the load, I got a max current output of 1.78A however the voltage sagged to 11.8V. at 50V input voltage. This current value corresponds exactly to the datasheet figure shown below. To increase this maximum current I could connect a 68uH inductor instead.
(https://i.imgur.com/vvBvI5r.png)
When I switched on with the load connected, the voltage only reached around 6.7V. I also connected a 1000uF cap on the output as per the datasheet to no effect.
However I don't think this is really an issue however, since on strat up I have really low current demands since only the logic need power. Then when I start running the motor at no load, all the circuit current is around 1.8A including the motor hence we can say that the buck current is negligible since most of the current is going through the motor and not the buck.
You can definitely try that, but I'd recommend trying to find the actual cause of the problem instead. I'd recommend you to run at half DC link voltage, probing all possible signals for over/undershoots. Then scale up.
Tomorrow I will replace the regulator on my board and test it using the scope and a limited power supply a Siwastaja suggested. I will move up in voltages until I see a problem.
I just remembered that when I was soldering the circuit, I soldered C7 (63 Volts capacitor for the input of the buck) backwards and it obviously blew. I replaced this and the buck worked fine,. Could I however when I blew the capacitor stressed the buck converter and put it on the edge of failing and after running it for a few minutes later it finally failed?
Thanks for all your help it is much appreciated.
-
So I tested the standalone Chinese buck converter board. I connected a load resistor of around 8.4 ohms at 15V buck setting, with a 100uH inductor. When I switched on the buck first and then connected the load, I got a max current output of 1.78A however the voltage sagged to 11.8V. at 50V input voltage. This current value corresponds exactly to the datasheet figure shown below. To increase this maximum current I could connect a 68uH inductor instead.
(https://i.imgur.com/vvBvI5r.png)
That is completely wrong. Y-axis on that graph is not volts, it is E.T (volt.us). You have to calculate it, in your case it is (48-15)*(15/48)*(1000/52) ~= 200.
So for a 1.75A load you need a H470 inductor. Look up the specs for that in table 4 and you'll have your inductor criteria. (In your case you could actually use Figure 30 (fixed 15v) as you are setting for 15v)....and you really should have a good idea of how much current you will be drawing on the 15v rail if you are at prototyping stage.
Using too small an output capacitor (within reason) will just result in more ripple. Stick your scope on it under load and see.
There is a detailed design procedure in the datasheet starting at page 21.
-
I completely agree with what you said. Upon further reading yesterday I came to the same conclusions. However as I was looking through the datasheet, I noticed that depending on the inductor size, you need a minimum value of output capacitor to ensure stability as seen below
(https://i.imgur.com/eeFSMx6.png)
So in my case I have a 100uH inductor. The minimum value for my capacitor would be as follows:
Cap out > 13300*((52V Vin Max)/15V*100) = 461. uF.
Now in my design I was using a 220uF cap on the output so that puts my pole pairs in the unstable region. I guess this is probably the cause of my buck converter working a lower voltages and failing at a fully charged battery i.e. 52V, since the highervoltage also effects stability. Therefore now I connected a 1000uf capacitor on the output that is more than twice the calculated value so it should be fine.
Today I tested it for 30 minutes under no load. Tomorrow I will test it with the motor connected with a supply. I wil take waveforms on the output of the buck and the gate drviers. Than I will do the same with the battery connected.
Hopefully the capacitor stability was the cause of my problems.
Regarding the fixed 15V model . I tried to find the 15V SMT model on mouse however I could only find the 12V and lower model. Hence that is why I went with the ADJ version so it would still be SMT.
-
Regarding the fixed 15V model . I tried to find the 15V SMT model on mouse however I could only find the 12V and lower model. Hence that is why I went with the ADJ version so it would still be SMT.
I meant that you can use the graph (Figure 30) intended for the 15v version to avoid calculating E.T for different input voltages.
100uH is much too small with your input voltage. look at E.T = 200 on that graph (Figure. 31). Even at 3A you need at least 330uH.
I suspect your peak load is more like 1A and that results in a 680uH inductor.
These old 52khz switcher designs need comparatively large inductors.
What is your actual peak 15v load?
Note. E.T = (Vin-Vout)*(Vout/Vin)*(1000/khz) = (48-15)*(15/48)*(1000/52) ~= 200.
-
I calculated that I have an average current consumption of around 250mA-300mA at 15V at worst case, Probabbly more like a 100mA. However The gate drives need around 1A peak tough that should be handled by their respective capacitors.
Can I assume around 1-1.5A current consumption to be safe and design around that? Since the graph we are referring to is stating Maximum current, and on start up, to charge the elec caps there is a significant draw.
That would mean around 680uH to a 470uH. However let's say my circuit is on stand by, and running at low current, I would fall out of this spec, would it risk destroying my buck converter? I think the inductor would operate in discontinuous mode, which is still fine for this converter according to the datasheet
Thanks for your help ;)
-
I calculated that I have an average current consumption of around 250mA-300mA at 15V at worst case, Probabbly more like a 100mA. However The gate drives need around 1A peak tough that should be handled by their respective capacitors.
Can I assume around 1-1.5A current consumption to be safe and design around that? Since the graph we are referring to is stating Maximum current, and on start up, to charge the elec caps there is a significant draw.
That would mean around 680uH to a 470uH. However let's say my circuit is on stand by, and running at low current, I would fall out of this spec, would it risk destroying my buck converter? I think the inductor would operate in discontinuous mode, which is still fine for this converter according to the datasheet
Thanks for your help ;)
That switcher has current limiting but you would want to ensure that your inductor will not saturate (especially give your large voltage delta). I wouldn't consider ephemeral current draw in inductor sizing as then you'll only be in continuous mode for microseconds. I don't think I've ever killed one of those simple-switchers, they're quite robust.
It's a balancing act to optimize for wide ranging operating conditions. Though I suspect your operating window is smaller than you think as peak draw at gate drivers will be provided by their respective capacitors and the average load on the DC/DC will be lower.
Since you have the rest of the board populated, you could hook up a lab supply to the 15v and actually scope the current draw.
If the load is low enough, this switcher will skip cycles while waiting for output voltage to fall below set point (discontinuous mode).
A higher value inductor will mean that the minimum current will closer to your average current, possibly avoiding discontinuous operation, at the expense of a larger and more expensive part.
Discontinuous mode is perfectly fine if the additional voltage ripple is acceptable.
The graphs for inductor selection are for continuous mode operation with certain assumptions on desired inductor ripple. I suggest you do some calculations, I wouldn't want to put a big expensive inductor in there...AN-1197 is a good intro.
have a quick read of 8.1.2 Inductor Selection
AN-1197 - Selecting Inductors for Buck Converters from TI is also informative.
http://www.ti.com/lit/an/snva038b/snva038b.pdf (http://www.ti.com/lit/an/snva038b/snva038b.pdf)
Good luck!
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Thank for the great info. Yes this regulator has a fairly low switching frequency, in the future I'd possibly change over to the TPS54160 since it has a much higher switching frequency leading to a small and cheaper inductor as you say. Also the chip itself is cheaper.
This morning it tested it out with a 680uh Inductor and it worked a treat!, even under around 110mA (no load) (i.e. discontinuous). The voltage was perfectly stable since I had a 1000uF cap on the output. It was at my maximum possible voltage (approx 52.7V). Here it is on startup.
(https://i.imgur.com/b7xAtqg.png)
I will test it will test it at full functionality i.e. with the motor as the gate drives get shipped since I want fresh ones (got some paranoia about using desoldered parts).
Thanks so much for your help!
As for future testing, apart from the double pulse test, I want to do a load test for the motor. I am looking at doing it cheaply. I am thinking of coupling a car alternator to the motor, I will apply a DC voltage to the Rotor of the alternator to create that magnetic field. I will short the 3 phase windings to create the load. As the rotor rotates, the alternator should start loading the motor. At low speeds should be less.
Meanwhile I will be monitoring the currents. The specification is a maximum draw of 20A from the DC supply (DC link). So I will stop at that point. I will be using a thermal camera to monitor the FET Temps. I will also vary the switching freq at 10Khz, 20kHz and 30kHz to see the effect of the switching losses on the FETs and if they come close to the simulation
Will keep you guys updated
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No need for the alternator. Lock your motor's rotor, that's the hardest load you can put on it, and it's a realistic load if you'll be using it to drive land vehicles. Your controller has to survive this "indefinitely" according to the specs you designed it for (X phase current).
This is the same setup you can use for the double pulse (I use it for both tests).
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Well that is certainly simpler! That the hardest test you can put on it definitely. However definitely have to have a very good current control loop at locked rotor.
How did you do your current control? Cycle by cycle or did you use a fixed control loop frequency? I was going to implement a current control loop of around 1.5kHz in a timer interrupt of the highest priority, so that the sampling period is always fixed.
PS I really appreciate all your advice! Thanks!
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Cycle by cycle, I think you have to do it cycle by cycle to protect the power switches. There are a few microcontrollers these days that even have some hardware specifically for that. It's a simple mechanism; start monitoring the current at the PWM cycle start, and force the cycle to end if the current reaches the maximum value you want to allow. Next cycle it all repeats. That's it.
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I understand the concept you are talking about but I am still not sure about some things.
I will use my MCU ADC in burst mode and whenever I reach my maximum DC link 20A I will stop the PWM.
I only have one current sensor on the DC link and from the explanation below, I can just use that for my current sensing since I like to keep things a simple as possible. Also I only have 4 ADCs on my MCU. Using 1 for a throttle input, 1 for the DC link and I'd like to add temperature sensing. Hence I cannot really sense 3 phases and have temperature sensing so I think DC link is the way to go
https://e2e.ti.com/blogs_/b/motordrivecontrol/archive/2016/01/21/protect-your-bldc-motor-drive-with-cycle-by-cycle-current-limit-control-part-1
Hence I would put the DC link sensor after the DC link capacitor and I think that would be fine. Other wise I would could add 2 current sensors on 2 of the phases that would also suffice.
I have the ACS733 Current sensors. They have an over current setting pin and a fault pin. I could connect the fault pin to and external interrupt and hey presto we got a winner for my maximum current limit. For my current set-point, I can just burst scan my adc and use that! as you described previously!
It's quite simple and faster the PID
See any potential flaws in my reasoning?
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The simplest thing you can do is to use a voltage comparator to trigger an "overcurrent" interrupt where you end the PWM cycle (some microcontrollers, even 8 bits ones like some AVRs, have this connection in hw and stop the PWM for you). For this you should measure the phase (motor) current. Due to the DC link capacitors, if you only have a current sensor on the battery side, that sensor will not tell you the whole story.
How to do it exactly depends on how fast and resourceful your uC and hw is. I have done in controller (for a DC motor) exactly what you mention, I put the current sensor after the DC link capacitors. So I can see the phase current, but only during the ON part of the PWM cycle - this means the ADC reading and PWM must be synchronized. I trigger the start of an ADC reading at the start of the ON cycle to measure the current (your PWM frequency should be such that the motor phase current ripple is small), but I have the voltage comparator to end the PWM cycle earlier if necessary.
In my case the uC was very small (8 bit, 2KB flash) so didn't have the resources or speed to do it all with an ADC input, and I still had other things to measure with the (single) ADC. I take ADC measurements round robin (motor current, DC link voltage and 2 temperatures), but the 1st one of the round is always the motor current, so I can synch it with the PWM (I was only able to take a current measurement every X PWM cycles but that's ok because it's still many times a second, current doesn't change that much and I have the voltage comparator mechanism to limit the current cycle-by-cycle).
Is the ACS733 fault pin current configurable? Because you'll want to set your own (motor phase) current limit. Your uC probably has a voltage comparator you can use for current limiting.
But, however, if you're controlling a BLDC, you'll need to measure current at least in 2 phases if you want to do something better than "3 phase commutation", such as FOC and the like.
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Unfortunately my Uc does not have this functionality.
I understand that to implement FOC I need multiple current sensors. I am still undecided on whether to go with one current sensor after DC link cap or on 2 phases. I think one is the way to go since it will be easier on the MCU and since my minimum sampling rate possible is 2.44us (pretty slow I think, but it will suffice I think)
The ACS has a configurable over current setting however it only ranges from 0.5 to 2 times the maximum current it can sense (40A) so I cannot use the fault pin at currents any lower than 20A so I will use that as my hard current limit with external interrupts. I could use other current sensing ICs that can do this however I would lose my Isolation.
I think my best option right now is to use one ACS on DC link. Use burst mode sampling for my set point and its fault pin for my hard limit.
Regarding synchronization, I can continuously be burst sampling my ADC. Upon each completion of a sample, the MCU will give me an interrupt and I can check whether it is over my threshold. Hence I would not have the problem of synchronization. Correct?
Hence I'd have the following interrupt with the highest having the highest priority.
Priority 0 - Fault Pin (External Interrupt)
Priority 1 - ADC sample complete (Current)
Priority 2 - Capture inputs for rotor position. (Hall sensors)
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If you put the current sensor before the DC link caps, you will not know for sure the phase current (can be estimated, knowing the PWM duty cycle), and you will not know the current "now", because there will be a delay for the controller input current ("battery current") to "catch up" with the phase current - will be looking at the average current. Some cheap Chinese ebike controllers do this. Note that the phase current can be 4, 5 or more times the battery current. So, if you only have a battery current sensor, there's not much rush setting a current limit, because the reading will not be "exact" nor "actual" anyway... so you can probably just go with the ADC readings, but since the implementation cost of the Fault pin is low so you might as well try.
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I plan on putting the current sensor after the DC link as seen below
(https://i.imgur.com/ZE71y8k.png)
In this configuration the current I will be sensing should be the "phase" current. And hence I know the current exactly all the time by scanning continuously the ADC and avoiding the synchronization issues
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No, you must synchronize the ADC readings. The current at that point will only flow during the ON part of the PWM cycle.
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Hi, interesting thread!
I am just absorbing all I can right now as I have been diving into writing firmware for bldc controllers. Anyway I have a bunch of hardware designs for speed controllers here in case its of any use. They have all been field tested ( literally.. each one goes in a rc car or quad and goes out to a field to drive around). Every post has gerber files, schematics and diptrace source files.
https://www.rcgroups.com/forums/member.php?u=696658 (https://www.rcgroups.com/forums/member.php?u=696658)
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Wow they look super interesting! Especially the SMT32F0 one!
While I was waiting for the gate drivers, I was busy deigning my final prototype (for now) the P3. Quite happy with the overall design, especially with how close I got the drivers to the fet inputs (using an embedded full bridge MTI85W100GC) shown on the bottom of the board. Included better current snesing as explained above with nuno (thanks!) and temperature sensing. The NTC temperature sensor will be connected to a 3mm aluminium plate which will be on the ceramic heat plate of the bridge module, which should give me aplenty of heat sinking.
Also fixed some design flaws I had with the Buck converter, optimized some component values, and as nuno suggested, to reudce the inductance I replaced my big dc link through hole caps with SMT ones which I luckily could get to ft in the limited space hence keeping the same incapacitate as my big through hole ones, which should give me better results.
(https://i.imgur.com/EzbaCkN.png)
(https://i.imgur.com/jhonoHm.png)
Today I soldered my fresh gate drives and I am planning to test again tomorrow. Hopefully I should have ironed out all my issues with the P2 barring any major oversights. I will also take some reading across MOSFET Vgs Vds. As you guys have suggested, I plan on soldering the ground lead to the fet and using that to reduce the scope inductance to produce the true results. Are there any more places which you guys should suggest I probe?
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Hi all so it took a while but I took some waveforms of my FETs.
So here is my setup as you guys recommended , I used a ground spring on my probe as seen below.
(https://i.imgur.com/12Uke6k.jpg)
(https://i.imgur.com/Db1R5vu.jpg)
Below are is my Vgs on the high side FET
(https://i.imgur.com/l8aTI7J.png)
(https://i.imgur.com/iwCs5Fi.png)
(https://i.imgur.com/91RjAtx.png)
There are the Vds on the high side FET
(https://i.imgur.com/kQ1b6qy.png)
(https://i.imgur.com/7vPokgY.png)
(https://i.imgur.com/eCzCecx.png)
Granted I took these waveforms running the motor at no load however having no overshoot/ringing at all is encouraging. Once I have my rig set up I will retake the waveforms under load.
Also yesterday as I was soldering the ground probe to the fet, I used solder wick and I didn't see that a strand came off and shorted out my source to drain. I switched on the circuit and poof the fet literally caught fire. I replaced it and everything worked fine. So that gives me a lot of confidence in my gate drivers, that they survived that since its the worse possible condition to operate under. I also probed on the gate driver pins over the bootstrap pins and my the voltage stay pretty much at 15V constant since I have a large 22uF elec cap in parallel with the ceramic ensuring, that I eliminate the problems of under voltage at those pins!
Also I tested the controller running constantly for 30 minutes at full speed an it worked fine so I seem to have resolved the issues with the Buck Converter
Any thoughts?
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So far looks good to me. You can do the same for the low side, for reference.
That's it, that's the right measurement setup.
Now let's see it under load ;)
v = L di / dt
Start with smaller currents and/or supply voltage (smaller current is easier, as it's just about adjusting the 1st pulse ON time on the double pulse test). Don't do the test repeatedly, do only one double pulse, on demand.
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Yup I will do it under test to see how good it really is :D
Just u question about the cycle by cycle current limiting. You said you need to sync it to the PWM on time. However, why can't you just scan the DC link current continuously (after the DC link capacitor therefore it is essentially the phase current.)
Wouldn't the highest point of the current be when the PWM is on and when it is off, the current would decay? Or is there a point I am missing?
I am not speaking about the double pulse test, but about current limiting in general
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After the DC link capacitors, the current is zero when the FETs turn off and the phase current when the FETs turn ON (trapezoidal). The decay you're thinking is probably the one in the motor.
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Woops I misspoke you are right about the decay. However just for regular current sensing I can just scan continuously the ADC and the highest point on my current sensor (R2 of your image) will be when the MOSFET is on since when the FET is off, the current will fall to 0 and that make my code a lot simpler.
I say this because my MCU is quite old and while it syncs to other timers, it cannot sync to my PWM timer. So while I will not be measuring the actual motor current in the FET off period, this will not be important to me since the max current experinced will be when the FET is on.
The MCU I am using is quite simple to program, however it doesn't have a lot of features. I plan to switch to a new MCU after these iterations of my project. I am currently using the LPC2119, however I also own an STM32F4vg07 so I could use that in the future. However I will look up the best MCUs for driving motors since they can have some added features which will be very useful.
So to summarize according to my methodology above I can continouasly scan R2 correct?
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Nice thread! The more I read, the clearer it becomes I chose the wrong major (chem), now trying to catch up all I can in electronics. My own design is for a pretty high-torque BLDC servo, I'm sure I'll find many interesting tips in this thread.
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I'll throw my $0.02. Granted that $0.02 has been hard earned from many hours of fires and "maybe if i stare at this scope capture long enough something will happen".
I'll also say that I get pretty excited about motor controller work and I skimmed your thread to get to the point of being able to reply. I know that sounds horrible and ill informed but I hope it provides some ideas. So here we go.
The idea of using a snubber system to quell output ripple is sound in theory. In practice with the types of power levels involved with motor control, it's difficult to really see through to fruition. If output filter must be used, try getting some blocking ferrites inline or around your motor output phases. These are very effective. Otherwise look to the other side of the FET. How is it being controlled? It may be doing exactly what your telling it to, and the ripple is a byproduct of the switch event - which of course it is.
Here's how I approach smooth switching for motor control applications.
- What does your FET driver power source look like under loaded switching conditions? Is there a lot of ripple and hash back up the 12v (or 15v) power line? If there is do your best to isolate that power line with possibly a ferrite at the output(meaning physically close) of your PSU, followed by SMT decoupling caps at each gate driver. You need clean power to switch cleanly. But if your switch event is out of control, no practical decoupling will calm 12v/15v line down.
- Lets look at the FET switching event! I see you got a scope with a short ground clip and took a quick grab of the Turn On/Turn Off events. But man, that's a 30,000ft view! Get down in there and take a peak through the Miller time (that flat spot during the turn on). What does that look like? Even from the 30,000ft view i can see it's a roller coaster. So what can we do about it? I think you're half way there with gate resistance and a gate snubber cap, but that snubber cap can just be a source of energy for a resonant system. lets calm it down with a 1-2 ohm resistor between the Cap and the Gate of the FET. Ultimately this is a T network with your ~10 Ohm Gate R on the left of the T, your Cap on the vertical of the T,
and a Series Resistor on the right of the T. Keep this all as physically close to the FET gate as reasonable, specially the cap and the series resistance. The 10ohm Gate resistor is not a bad place to start. You could do some modeling w/ your FET's gate capacitance, PCB parasitics, and driver system. But laying it out and hitting it with a scope is more fun ;) - You already found the caveat of Gate driver's and their switched node negative voltage transient susceptibility. So you're really digging into datasheets. A 1-5 ohm resistor in series with your switched node as close as possible to your Gate Driver should quell the transient here. With good layout, and reasonable motor currents this shouldn't be much of an issue. But a 1 ohm doesn't harm you much and does a lot to guard the Gate Driver from a fault or failure. It does slows down your high side boost cap's recharge time a bit, and add's in series with your gate resistance really effecting your turn off more then turn on event.
Now you have the elements in place to really tackle the FET switching event.
Ensure your dead times are adequate between devices before examining FET switching behavior. -If complimentary PWM is in play.
Next go through and bring the system up to a low load, not no load, but low load. Things just bounce around under no load and the FET Gate transients don't quite show as well. Get something like 1/10-1/5 your expected load going on the motor and use that snub scope probe to closely look at your FET Vgs during turn on and turn off. Get down in there and get a good clear view of your Miller time - When the FET Vgs rises, then goes almost horizontal for a bit then continues to rise in a typical RC charge fashion. That Miller time should be smooth and controlled. You shouldn't see ripples and roller coasters here as they'll directly translate to your output.
With the gate snubber cap removed, bring your Gate Resistance up to slow down the FET switch event and try to calm out the big waves in the Miller event under some mild load. Ensure you don't extend the transient time to overlap with your deadtime and cause shoot troughs (again, complimentary PWM only). Really watch your FET temps. Once those start to increase rapidly, bring your Gate Resistance back and start adding gate snubber capacitance to your T network in low nF region to start. I've found this capacitance to be incredible effective to calm the switch event. Ensure your measuring Vgs on the FET legs itself. Experiment and walk around your snubber capacitance value and gate resistance value. Keep the series resistance low at 1-2 ohms to keep the snubber capacitance in the game, you don't want to raise that resistance and decrease the effectiveness of the added capacitance, you just want to slow down that fast MLCC.
Start to walk your load up and watch how the Miller event changes. Higher FET current, longer Miller event and generally less stable. Adjust as needed, keeping things fast for thermal performance, but smooth for noise.
Get Your high and low side Miller events as close as possible. This will very likely require different value Gate Resistors. You'll likely be able to keep the capacitance the same, and keep your series resistance the same.
Now take a look at your Gate Driver voltage supply rail, has that calmed down? I bet it has.
How about your Vds switch event? Little smoother now? I've found AC coupling to work a treat here to really get a good view of the noise during that transient.
Looking down to your phase outputs if there's still noise being emitted, throw some ferrites around it and call it a day! (hopefully! ;)
I hope that helps, and isn't muddying the water with other options offered in this thread. Like i said i didn't read everything but i think i got a decent grasp of what was done. And let me know if some of that isn't clear. I can draw up a simple schematic or the like later if needed.
Oh! and keep the bulk electrolytics! If you run only MLCC for your main bus capacitance it'll be way to fast and cause all sorts of nasty voltage transients. Place some resistance in series with the MLCC bank if you must go this route. Now, "some" MLCC in parallel with the bulk electrolytic is a good move, just watch your Vds transient as you add more. And of course power planes and de-loop every nook and cranny you can!
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Hi,
Thanks for all the info! My the Miller time I guess you mean what's called the Plateau voltage on most Application notes?
Regarding the negative transients on the gate driver I measured it between Vboot and Vs and I am not getting any at all. You can see these shots on the first page of this thread (the ringing there is because I did not use a ground clip). This is because I have added a 'large' elec cap (22uf iirc) in parallel with my cermic bootstrap cap (0.470uF iirc) and this give me no ripple at all I also have no ripple on my 15V supply.
Here id you 30FT view of the switching event (Vgs) ;)
(https://i.imgur.com/dUObOkm.jpg)
There is a bit of a dip in the turn on which I don't know where it comes form.
I was running at a low load (i.e. motor, but motor is not load around 1A DC link current).
Regarding the T network I decided to forgo the gate snubber cap to reduce component count, size and length of traces, and I doesn't look to bad also the cap would slow down my switching correct as I dont want any shoot-through?
I also do not have a resistor with the positive of the bootstrap cap it just feeds in directly. Because of the elec boot strap cap in parallel I do not get any (almost any) reduction in my voltage.
I set the deadtime with the gate driver around 333ns using an external resistor.
I will run tests under load when I finish building my rig :D
With regards to the Elec Caps, on my new board, I have found some sexy SMT ones with the same capacitance which I just managed to squeeze on the board and that eliminates the 'LEAD inductance" of the capacitor legs since I left them long to bend them over.
Regarding use of the ground clip, I have soldered it to the fets and I just hold the probe to the gate, do you know of any tricks to avoid shorting pins with the probe if you hand slips for example, I used some tape but I'd still like to make things safer so I don't blow stuff up while measuring.
Thanks for all the detailed info you seem to have ALOT of experience. I really love power electronics an motor drives (minus the blowing up and catching fire of stuff as you said)
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Yes the area to the left of your Vgs curve is the Miller event/time/plateau. This is the linear region of the FET. Any modulation here is amplified to the output. Power Switch FETs do not like to hang out during this time, they're made to blast through it and get into the enhancement region and have a low Rds. Wiggles are bad here IMO. One could make the argument that a fast turn on with a wavy Vgs through the Miller event is okay. It essentially only adds noise, your thermal performance is better the faster u switch. But that noise will get you so i recommend a nice controlled switch.
Just google "FET miller event" and take a look at those top app notes and other info. Lots of good things there.
Get some load under the controller to really see what's happening. Even making a Wye connected Power Resistor arrangement and telling your controller to blindly commutate @ some predefined duty cycle is a great way to get safe current flowing through the system. Bypass whatever phase angle/commutation state system your using has have it tick through all the phases as if it was running the motor at 60RPM or some such number. Or if you're running off hall effect sensors. leave that portion of the motor hooked up and connect power Wye to the phase output and simply turn the motor by hand - with a limit on duty cycle, and appropriate resistance values of course!
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I am currently busy doing some write up on my thesis till I get my testing rig done.
In the mean time do any of you know of any good books, relevant to high power PCB design (i.e. inverters and similar items) and also brushless motor controllers with regards to more complex driving algorithms such as FOC and the like.
I'd like to read up a bit at the end of each day to lean more a go into more deatail. I have looked up a bit online but before spending my money I'd like to make sure it is relevant.
Thanks
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So after a long while of trying to get my rig sorted out, it is finally ready and here are my results.
Here is my Testing Rig. I decided to go with this type of rig since I can control the load applied to my motor quite easily. So the motor on the left is my BLDC motor which I am driving (Prime Mover). It is couple via motor couplings with a rubber piece in between to take away any misalignment and vibrations. The load on the right is a modified car alternator. I have shorted out the start wingdings together. To control the amount the motor is loaded, I apply a DC current to the rotor through the brushes. At around 2A rotor current (to the alternator) the BLDC motor is loaded at 20A phase current.
I think it is a pretty good setup for varying the motor load. Getting the motors coupled together was the biggest issue.
(https://i.imgur.com/go8VJjM.jpg)
So here are my results. This is the Vds voltage at 20A phase current. This is basically at my maximum set specifications and I was pleasantly surprised. There is some voltage overshoot but I think it is within reason. What do you guys think?
(https://i.imgur.com/JDIfbmM.png)
Here is the phase current of one of the phases. This is just under full load
(https://i.imgur.com/RqvGmcr.png)
What do you guys think of the performance? I think it is within reason.
Soon I will get the thermal camera and will run thermal tests but even at 20A for a few seconds the FETs did not even get warm but I will run the test for a couple of minutes to ensure steady state is reached.
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Your 28% overshoot looks quite reasonable to me. (Assume it's a bit more due to scope BW limitations.) Unless you are aiming for absolutely minimized EMI, this is probably as good as it gets. RC snubbers could make it even better, but with efficiency cost. (Sometimes it also happens that your layout is already so tight, that there is simply no room for RC snubbers without making the layout worse again, in which case their effectiveness is less than expected.)
Many "rule-of-thumbers" tend to overrate the Vds(max) by 50% from the maximum DC link voltage. If you do this, you seem to be well covered, especially if the MOSFETs are avalanche rated so that tiny little peaks over the Vds(max) won't instantly kill them.
If I read the timescale of your trace right, the oscillation happens at around 60-70MHz and dissipates in two cycles. Frequency this high suggests fairly tight loop.
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Yes I think it is pretty satisfactory especially considering my first board layout.
While EMI are not major considerations for me, does the overshoot cause significant EMI and if so how exactly? (Still trying to get a decent grasp of the EMI concept, issues etc.)
You were pretty close on the reading I just measured the frequency and it is 58.8 Mhz oscillating frequency.
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The overshoot also seems pretty reasonable to me, and the oscillation is dampen quickly. I think the military/aerospace have tighter requirements, but that's not your case.
I can't comment on the EMI, but mind that it's the current changes that emit.
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Thanks for the feedback. I'll update you guys with some shots of he thermal performance when I acquire the thermal camera
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So here are my Thermal Results
I ran the tests at Multiple switching frequencies 30kHz, 20kHz, 10kHz and a load current of 20A for all tests. The temperatures were allowed to reach steady state. Interestingly the it took quite a long time for steady state, around 15- 20 minutes which was more than I predicted.
This is my control an ambient temperature of toughly 23 degrees
(https://i.imgur.com/WoHY5kA.jpg)
30kHz:
(https://i.imgur.com/v2Fh9n3.jpg)
Low side FETs
20kHz:
(https://i.imgur.com/wMVcjen.jpg)
Low side FETs
(https://i.imgur.com/vlFa7yk.jpg)
High Side FETs
10kHz:
(https://i.imgur.com/SxXUsdo.jpg)
Low Side Fets
(https://i.imgur.com/Kqvb88O.jpg)
High Side Fets
(https://i.imgur.com/dMbORst.jpg)
Load Motor (Alternator) got very hot as can be seen ended up putting a desk fan on it and that dropped the temperature by a few degrees (to around 100)
I think the results are quite interesting, there is a major difference between the 30 and 20kHz frequency but roughly no difference between 20 and 10kHz. Also due to the low and high side FETs being directly on top of each other their temperature was practically identical. The phase wires also got warm, I guess they added as a heat sink as well.
The DC link capacitor got warm but nothing major.
Any thoughts?
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Right so the data did not really sit well with me, I did not like that the 10kHz and 20kHz were at the exact same temperature. So I ran all the tests again and allowed ample time for the FETs to reach steady state. Ant the results were better and made more sense
(https://i.imgur.com/nbt0esA.png)
While at 10kHz the FETs ran the coolest, significant Motor "Whine" was introduced which is VERY annoying and unacceptable in my eyes. At 20kHz no audible noise could be heard. My original switching frequency was 30kHz so I have now moved to 20kHz which saves on a lot of losses and around 8 degrees of temperature.
I have also tested my P3 prototype with the integrated mosfet module and it worked fine. I will attach a 2mm aluminium plate as a heat sink and re run these tests.
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So Guys I finished my third design it is working well at full load but upon testing the Vds Voltage I spotted a problem!!! I need your expert advice
(https://i.imgur.com/VI5Z84t.png)
As you can see the spike on turn off is relatively low, but the spike on turn on is massive and it just does not make sense for me. I was probing on the high side fet as seen below. I was probing from VCC to phase using a ground spring.
I am thinking it might be an issue in the measurement setup. Could it be that because I am probing over the GND pin with the ground spring there could be some interference emitted into my measurement due to the high currents?
(https://i.imgur.com/1M4hbP6.jpg)
(https://i.imgur.com/gz94BI0.jpg)
It just does not make sense to me.
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Nice reporting of your project. I also seems to have spikes on battery voltage when high current is flowing through the motor. Already using RC snubbers and TVS diodes to clamp them.