Is there anything wrong with my LDO design?

[technix]

I designed this LDO circuit as my two-stage high efficiency bench power supply project.

The general idea of the project is to combine the high efficiency of an SMPS with the low output noise of an LDO, by supplying the LDO with the SMPS regulating at 0.5V higher than the required output voltage, and use a LDO to smooth out the ripple. The specification I was shooting for is 30V 5A maximum, single rail.

Here is the LDO stage, grossly simplified. EE.SE folks told me that this design would not work, but from my breadboarding experiments they worked fairly well and even allowed me to shoot for a lower headroom (it is PMOS LDO after all, and the headroom can be really low if I push it)

Would anyone tell me if this design still need some rework?

[Kleinstein]

This circuit has trouble at voltages below about 5 V, as there is not enough voltage to drive the gate. Also the TL08x needs at least 8 V or so. Also stability is not that simple with the load at the drain. Also a good PSRR is not that simple for this type of circuit.
If one can use a higher supply for the regulator circuit, it gets much easier. The regulator circuit itself does not need much current, so it may run from the full supply (e.g. 40 V) or linear regulated 35 V.

[T3sl4co1l]

The gate is drawn backwards... it's supposed to leave the symbol on the 'source' side..

There is no compensation for a series of two voltage gain stages, so you're pretty much guaranteed oscillation.  It might not be high amplitude with the filter cap out there, but it most likely won't be stable.

Why choose a BS170 for the gain stage?  A BJT (e.g. 2N3904) would be better, with a quite large emitter degeneration resistor so that its voltage gain is small.

The IRF4905 will have over 6nF Cgs and Cdg, each.  R2 gives a time constant around 80us, which will dominate the loop's high frequency range.  Although Cdg is large, C2 presumably does a good job shunting rapid changes, so that Miller effect isn't a big deal.

Why choose TL081 for the error amp?  The voltage headroom is small, and the output voltage range is hardly even enough for a BS170, let alone the full range of the suggested BJT substitute.  Input common mode range is 3V from negative supply, includes positive supply; output range is 1.5V inside of both rails.  A RRIO like TLV2371 would be better suited, and by flipping the input terminals, can be used to directly drive the PMOS (well, with a modest series resistor).

To apply compensation, you'll need feedback from the dominant gain node.  As shown, you don't have one, you have two -- like I noted before, two voltage gain nodes.  This has to be compensated by making one much faster, or one much slower.

The "one faster" route would involve, first, driving the PMOS with a complementary emitter follower buffer, so the  BS170 drain voltage swings quickly and freely.  Then making it proportional, by applying shunt feedback (series resistor from op-amp output to BS170 gate, resistor from gate to drain), or current feedback (source degeneration), to stabilize the voltage gain at a modest level, perhaps 1-3 x.  As mentioned, a 2N3904 will be easier to work with.

The "one slower" route would require running the error amp at low, proportional gain, and actually using the BS170 as the compensated error amplifier.  Its gain node is already slowed down, so as long as total loop gain is modest at high frequencies, it won't oscillate.  The dominant capacitance of the PMOS gate will give plenty of phase shift, though, so that not much phase shift can be tolerated elsewhere -- likely, C2 will need ESR such that the zero formed at C(C2) * R(C2) has the same time constant as the gate.  80us/220uF = 0.37 ohm, which isn't unreasonable for an electrolytic.



Tim

[dom0]

stability is not that simple with the load at the drain.

Meaning, stability is never simple with classic LDOs, since capacitive loads (or, actually, their ESR) will always be troublesome.

[technix]

The gate is drawn backwards... it's supposed to leave the symbol on the 'source' side..

There is no compensation for a series of two voltage gain stages, so you're pretty much guaranteed oscillation.  It might not be high amplitude with the filter cap out there, but it most likely won't be stable.

Why choose a BS170 for the gain stage?  A BJT (e.g. 2N3904) would be better, with a quite large emitter degeneration resistor so that its voltage gain is small.

The IRF4905 will have over 6nF Cgs and Cdg, each.  R2 gives a time constant around 80us, which will dominate the loop's high frequency range.  Although Cdg is large, C2 presumably does a good job shunting rapid changes, so that Miller effect isn't a big deal.

Why choose TL081 for the error amp?  The voltage headroom is small, and the output voltage range is hardly even enough for a BS170, let alone the full range of the suggested BJT substitute.  Input common mode range is 3V from negative supply, includes positive supply; output range is 1.5V inside of both rails.  A RRIO like TLV2371 would be better suited, and by flipping the input terminals, can be used to directly drive the PMOS (well, with a modest series resistor).

To apply compensation, you'll need feedback from the dominant gain node.  As shown, you don't have one, you have two -- like I noted before, two voltage gain nodes.  This has to be compensated by making one much faster, or one much slower.

The "one faster" route would involve, first, driving the PMOS with a complementary emitter follower buffer, so the  BS170 drain voltage swings quickly and freely.  Then making it proportional, by applying shunt feedback (series resistor from op-amp output to BS170 gate, resistor from gate to drain), or current feedback (source degeneration), to stabilize the voltage gain at a modest level, perhaps 1-3 x.  As mentioned, a 2N3904 will be easier to work with.

The "one slower" route would require running the error amp at low, proportional gain, and actually using the BS170 as the compensated error amplifier.  Its gain node is already slowed down, so as long as total loop gain is modest at high frequencies, it won't oscillate.  The dominant capacitance of the PMOS gate will give plenty of phase shift, though, so that not much phase shift can be tolerated elsewhere -- likely, C2 will need ESR such that the zero formed at C(C2) * R(C2) has the same time constant as the gate.  80us/220uF = 0.37 ohm, which isn't unreasonable for an electrolytic.



Tim

Can you suggest some jellybean RRIO that is available in DIP packages and is cheap ($0.5/each or lower?) Or I will have to stick to what I have: TL08x, LM324, LM358 and OP07. I actually also have a few NJM4559, NE5532 and OPA2134 leftover from my mixing console project, which probably won't be a good choice.

About the slow route, will hooking a negative feedback resistor to the op amp to bring the gain down a good idea? My simulation tells me that hooking a 1k resistor across there reduced oscillation to 100uV with the same frequency as the input. Does that means I killed the oscillation?

[technix]

This circuit has trouble at voltages below about 5 V, as there is not enough voltage to drive the gate. Also the TL08x needs at least 8 V or so. Also stability is not that simple with the load at the drain. Also a good PSRR is not that simple for this type of circuit.
If one can use a higher supply for the regulator circuit, it gets much easier. The regulator circuit itself does not need much current, so it may run from the full supply (e.g. 40 V) or linear regulated 35 V.

The final product will have auxiliary rails for op amps and digital controlling circuitry, and the choice of TL081 is not final (as I only have a few models to experiment with and the first came to me is TL084.)

[dom0]

Well a 5532 will likely have better dynamic behaviour, lower noise and offset than a TL0xx. It also drives heavier loads better than the very picky TL0xx. Of course only in the proper circuit...

[Kleinstein]

With a separate supply the OP08x is the least problem, and would be OK. Though an OP which is single supply capably is needed if there is no negative Supply. Driving a P-FET would already need a negative supply anyway. A good regulator will also like to have some minimum load at the output, not to have the output stage run at zero or very low currents.

The circuit looks over-simplified. The current measuring shunt is also missing. How the OP_amp is supplied is already an important part of the design choice. Also the type of preregulator may be important, as noise can be more on the positive or negative side.
With the rather high frequency emissions from a switching part some passive filtering is likely also needed. To get a low noise output is not just a question of the circuit plan, but layout and details of some components (like ESR of capacitors) is also important.

[free_electron]

with 30 volts input you are going to blow out the gate of the pass transistor if you want like 1 volt at the output.
VGSmax of a mos is typically 20 volts. ....

[technix]

with 30 volts input you are going to blow out the gate of the pass transistor if you want like 1 volt at the output.
VGSmax of a mos is typically 20 volts. ....

That is a separate thought (and I really don't mind using another TL431 chip or a Zener to clamp Vgs to 12V.) And if the output is 1V the input will be 1.5-2V. This PSU have a microcontroller in it keeping eyes on the voltages.

[technix]

With a separate supply the OP08x is the least problem, and would be OK. Though an OP which is single supply capably is needed if there is no negative Supply. Driving a P-FET would already need a negative supply anyway. A good regulator will also like to have some minimum load at the output, not to have the output stage run at zero or very low currents.

The circuit looks over-simplified. The current measuring shunt is also missing. How the OP_amp is supplied is already an important part of the design choice. Also the type of preregulator may be important, as noise can be more on the positive or negative side.
With the rather high frequency emissions from a switching part some passive filtering is likely also needed. To get a low noise output is not just a question of the circuit plan, but layout and details of some components (like ESR of capacitors) is also important.

The negative supply is there - auxiliary supply rails not shown here. The minimum load requirement is fulfilled by the output sampling divider resistors - noticed the low value resistors I used there? (I could have used 150k/120k but I used 1.5k/1.2k instead - there is a reason behind this.)

[Alex Eisenhut]

The gate is drawn backwards... it's supposed to leave the symbol on the 'source' side..

Maybe I can ask you, why do some symbols show the body diode as a Zener diode?

[T3sl4co1l]

The gate is drawn backwards... it's supposed to leave the symbol on the 'source' side..

Maybe I can ask you, why do some symbols show the body diode as a Zener diode?

Presumably, to redundantly show that the transistor is capable of withstanding avalanche.  It's pretty silly, in my opinion.  The wedge on the middle connection explicitly indicates the substrate connection, and substrate-channel junction, so the outboard diode is somewhere between superfluous and misleading (i.e., there is no actual separate diode).

In contrast, IGBTs do not posses an antiparallel diode structure (the device has a four layer SCR type structure instead), and therefore requires a true "co-pack" (a second die in the same package) to be operated in reverse.

There are "FETky" products which use a schottky diode, which I don't know if the schottky junctions are integrated on the same device, or co-packed as well.  Such devices could be indicated with a curly line diode symbol.  (However, a MOSFET channel actually made with a schottky junction is something different, a MESFET.)

Tim