Electronics > Projects, Designs, and Technical Stuff
Book for Gate Drive design and IGBTs
<< < (3/4) > >>
MagicSmoker:

--- Quote from: T3sl4co1l on July 25, 2019, 10:49:51 pm ---
--- Quote from: MagicSmoker on July 25, 2019, 10:45:49 pm ---I suspect you are assuming desaturation as a result of a cross-conduction type of failure, rather than a short in an external load (e.g., a motor or the primary of a transformer whose secondary is shorted)?

--- End quote ---

Either one.  I mean, the exact rate of rise in Vce depends on the V(I) curve and the fault inductance (so, dI/dt), so a more distant short may not actually go from 7 to 15V in 3ns.
--- End quote ---

I think you missed my point: the Vce[sat] for most IGBTs that are rated at 1700V or less is in the range of 1.2V to 3.0V, and it increases with Ic as one would expect for a bipolar device (that is, 60-120mV/decade of current, plus a bit more due to the various resistances), so triggering desat at 7V is needlessly abusive. For example, even if Vce[sat] is 3.0V at rated Ic, it will likely only increase to about 3.5V - 4V at 2x Ic, and maybe 4V - 4.5V at 3x Ic, etc., but once desaturation occurs - which could be anywhere from 2x to 6x rated Ic, depending on the precise construction of the die - Vce will shoot up rapidly, to the point that the device will act more like a constant current source. Triggering desaturation protection a couple volts lower than the standard 7V threshold isn't so much to grant the protection circuit more time, it is to reduce the peak power experienced by the switch. Besides, to make a reliable desaturation protection circuit you have to ignore Vce when the gate is first brought high for 200ns - 1us, anyway, to avoid false triggering.

That said, if the fault is cross-conduction of a half-bridge directly fed from a dc link capacitor then there is almost no hope of protecting the IGBTs, even if the Vce threshold is lowered to 5V, as fault current might very well zoom up to the desaturation-limited value even during the blanking time for the desat detection circuit, and then it's more a case of, "Abandon Hope, All Ye Who Enter," etc.


--- Quote from: T3sl4co1l on July 25, 2019, 10:49:51 pm ---But in that case, this more modest fault condition will be managed by normal operation of the current mode controller, long before reaching desat magnitudes, so I don't see that it's anything to be concerned about.
--- End quote ---

That assumes this is a power supply employing current-mode control, when it could be a power supply using voltage-mode control with cycle-by-cycle overcurrent protection, or a PFC stage using average current mode control, or a motor drive also only using cycle-by-cycle current limiting, or a motor driving using average current mode control and relying on desaturation detection as well as a peak-detector on a Hall-effect transducer for overcurrent protection, a UPS running a fixed PWM waveform without a control loop at all - you may shudder at this kind of sloppy design but I've actually seen it in a commercial product, etc.



--- Quote from: T3sl4co1l on July 25, 2019, 10:49:51 pm ---A typical design scheme is to have desat protection very close in (perhaps on the gate driver itself, with a feedback signal to halt the controller), then a current transformer (to measure load current) for normal feedback (control limiting/regulation/operation), with an overcurrent threshold so that if the controller can't handle it, it again halts.  (The desat signals can be wired-OR as a single fault signal, or individually latched to indicate possible service targets.)
--- End quote ---

Yep, this is a good plan of attack if your budget allows such a braces and suspenders approach (substitute a Hall-effect transducer for current transformer, where appropriate).

T3sl4co1l:

--- Quote from: MagicSmoker on July 26, 2019, 05:11:47 pm ---I think you missed my point: the Vce[sat] for most IGBTs that are rated at 1700V or less is in the range of 1.2V to 3.0V, and it increases with Ic as one would expect for a bipolar device (that is, 60-120mV/decade of current, plus a bit more due to the various resistances), so triggering desat at 7V is needlessly abusive. For example, even if Vce[sat] is 3.0V at rated Ic, it will likely only increase to about 3.5V - 4V at 2x Ic, and maybe 4V - 4.5V at 3x Ic, etc., but once desaturation occurs - which could be anywhere from 2x to 6x rated Ic, depending on the precise construction of the die - Vce will shoot up rapidly, to the point that the device will act more like a constant current source. Triggering desaturation protection a couple volts lower than the standard 7V threshold isn't so much to grant the protection circuit more time, it is to reduce the peak power experienced by the switch. Besides, to make a reliable desaturation protection circuit you have to ignore Vce when the gate is first brought high for 200ns - 1us, anyway, to avoid false triggering.
--- End quote ---

If it's rated for 10us of short circuit, what's the difference?  It still survives.

Lower and lower thresholds are more sensitive to errors, and prone to false triggering; and you want to avoid blanking and filtering schemes where possible.



--- Quote ---That said, if the fault is cross-conduction of a half-bridge directly fed from a dc link capacitor then there is almost no hope of protecting the IGBTs, even if the Vce threshold is lowered to 5V, as fault current might very well zoom up to the desaturation-limited value even during the blanking time for the desat detection circuit, and then it's more a case of, "Abandon Hope, All Ye Who Enter," etc.
--- End quote ---

Whose IGBTs are hopeless?



--- Quote ---That assumes this is a power supply employing current-mode control, when it could be a power supply using voltage-mode control with cycle-by-cycle overcurrent protection, or a PFC stage using average current mode control, or a motor drive also only using cycle-by-cycle current limiting, or a motor driving using average current mode control and relying on desaturation detection as well as a peak-detector on a Hall-effect transducer for overcurrent protection, a UPS running a fixed PWM waveform without a control loop at all - you may shudder at this kind of sloppy design but I've actually seen it in a commercial product, etc.

--- End quote ---

The predecessors to the designs I was working on, were basically wide open loop, old school, verbose logic designs.  They didn't even use oscillators, they slapped together a bunch of monostables to do it.  Lots of CD4000 or 74AC logic, on the premise that the higher voltage, or lower output impedance, provides noise immunity.  Lots of opamps, for reasons I never quite understood (only a couple are really needed, for a full analog+logic design of that capability).  The old guard laughed at our choice of FPGA with its 1.1V core; but go figure, they didn't know anything about EMC, they just cookbooked everything.

Point being, the gate drivers similarly were just that, a transformer to supply DC power, an opto to couple signal, and an IRF(9)540 H-bridge to drive the gate to +/-15V.  No desat protection (would be hard to implement with that H bridge output, anyway), no current sensing, aside from the one current transformer (common to all inverters in parallel) for feedback (phase and amplitude, this was a resonant system).  Controller terribly slow, dominant pole compensated, you could watch the dials as it started up (settling time in the fractional seconds).

So, needless to say, they burned a lot of transistors on those designs.  But service is so expensive that they really don't care about transistors as such, and operation is usually so consistent (industrial process equipment) that they can get years of continuous operation despite the dumb design.

There was also the even older generation of SCR inverter units, which I had nothing to do with, but saw them come in for service from time to time.  Think the controls were even more limited on those, but again they were only used on very stable loads so if it starts up once, and stops once, successfully, who cares...



--- Quote ---Yep, this is a good plan of attack if your budget allows such a braces and suspenders approach (substitute a Hall-effect transducer for current transformer, where appropriate).

--- End quote ---

Yes, which since we're talking $200 IGBTs here, the added cost is quite small, and the savings (to the customer) in service calls is huge.

Tim
Glenn0010:
I've started going through all of the materials you guys linked, and I'm going to be busy for a while! I've also been brushing up on the FET chapter of the Art of electronics (I am switching IGBTs but they are similar). It should help jog my memory back with anything that I may have forgotten
MagicSmoker:

--- Quote from: T3sl4co1l on July 26, 2019, 06:37:25 pm ---If it's rated for 10us of short circuit, what's the difference?  It still survives.

Lower and lower thresholds are more sensitive to errors, and prone to false triggering; and you want to avoid blanking and filtering schemes where possible.
--- End quote ---

It took me a couple days to get around to doing this, but I excerpted the relevant portions from a state-of-the-art IGBT datasheet to illustrate my points. Basically, if Vge is 15V and desat threshold is 7V then short circuit current for this "50A" rated IGBT is so far off the scale who knows what it will end up at (though, from experience, trench gate NPT IGBTs typically desaturate at 6x rated Ic). If the desat threshold is dropped to 5V and Vge is also lowered to 13V then short-circuit current will top out around 180A, just based on linear extrapolation of the graph.

This puts far less energy into any stray inductances which will complain loudly during the turn-off process, greatly reduces the peak power dissipation in the IGBT, and turns a lifetime-reducing event into one that is barely noticeable, all at the cost of about 0.1-0.2V of additional voltage drop during normal operation at rated Ic. I'm not even mentioning any theoretical increase in false triggering from lowering the desat threshold to 5V from 7V because it simply doesn't exist (not unless your layout is so awful that 5V logic won't work reliably, either).

In contrast, not inhibiting the desat detection comparator for at least as long as the sum of the turn-on delay and rise times will result in false triggering - you simply can't avoid this blanking time, though in this case it's relatively short (<100ns at 175C, though note that only typical values are given...).

max_torque:
Given that you work for a drives company, with i suspect a long history of making, er, drives, then the best thing you can do is to raid the archives i suspect, and find every gate driver circuit ever used by your company in a product.  Go talk to the service dept as well, and find out which drives had good reliability, and those that didn't, and find out what the primary in-service failures were caused by!

IMO, that will be worth far more than getting bogged down in possibly completely irrelevant theory!
Navigation
Message Index
Next page
Previous page
There was an error while thanking
Thanking...

Go to full version
Powered by SMFPacks Advanced Attachments Uploader Mod