Author Topic: Book for Gate Drive design and IGBTs  (Read 3459 times)

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Offline Glenn0010Topic starter

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Book for Gate Drive design and IGBTs
« on: July 25, 2019, 06:45:26 pm »
Hi all,

So as a graduate Power Electronics engineer, after a year working on various things in R&D of a drives company I get what I've been after! I am going to be designing the gate drives for our new product line.

I have already designed gate drives before for my bachelors thesis so I have a pretty good grasp of things. However I want to do the best job possible. Further more in the past we have run into some issues during short circuit testing so I'd like gather more information on how these can be sorted from the onset.

Are there any good books which talk specifically about IGBTs, FETs and gate drives. Things such as the Kirk effect and so on.

 Thanks for you help as I've been struggling to find books on such things.

Cheers
 

Offline MagicSmoker

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Re: Book for Gate Drive design and IGBTs
« Reply #1 on: July 25, 2019, 08:04:39 pm »
...
I have already designed gate drives before for my bachelors thesis so I have a pretty good grasp of things. However I want to do the best job possible. Further more in the past we have run into some issues during short circuit testing so I'd like gather more information on how these can be sorted from the onset.

Surely ("and don't call me Shirley"*) you realize this is rather open-ended - there's a wide range of gate drive designs of varying complexity w/r/t isolation voltage, power level, budget, switching speed, whether multiple switches will be operated in parallel (or, much less commonly, in series), whether dynamic current (or voltage) sharing is required in parallel (or serial) operation, hard-switched - so considerable Miller effect - or (quasi-)resonant, etc.

That said, the default desaturation threshold in many commercial IGBT gate driver ICs is around 7V which is almost always too high to save the IGBT when it is triggered; knocking a couple volts off that and setting the gate voltage when on to around 12-13V, instead of 15V, can improve the odds of surviving a hard short greatly (for NPT IGBTs, anyway; all bets are off with PT types). 

Are there any good books which talk specifically about IGBTs, FETs and gate drives. Things such as the Kirk effect and so on.

Not that go into any great detail, but plenty of app notes floating around the interwebz on this subject. I haven't thought about Kirk effect in years, but I do recall it is a property of semiconductor device physics and therefore not something you can do anything about.


* - 2 points to anyone who recognizes that classic quote
 

Offline Glenn0010Topic starter

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Re: Book for Gate Drive design and IGBTs
« Reply #2 on: July 25, 2019, 09:23:21 pm »
...
I have already designed gate drives before for my bachelors thesis so I have a pretty good grasp of things. However I want to do the best job possible. Further more in the past we have run into some issues during short circuit testing so I'd like gather more information on how these can be sorted from the onset.

Surely ("and don't call me Shirley"*) you realize this is rather open-ended - there's a wide range of gate drive designs of varying complexity w/r/t isolation voltage, power level, budget, switching speed, whether multiple switches will be operated in parallel (or, much less commonly, in series), whether dynamic current (or voltage) sharing is required in parallel (or serial) operation, hard-switched - so considerable Miller effect - or (quasi-)resonant, etc.

That said, the default desaturation threshold in many commercial IGBT gate driver ICs is around 7V which is almost always too high to save the IGBT when it is triggered; knocking a couple volts off that and setting the gate voltage when on to around 12-13V, instead of 15V, can improve the odds of surviving a hard short greatly (for NPT IGBTs, anyway; all bets are off with PT types). 

Are there any good books which talk specifically about IGBTs, FETs and gate drives. Things such as the Kirk effect and so on.

Not that go into any great detail, but plenty of app notes floating around the interwebz on this subject. I haven't thought about Kirk effect in years, but I do recall it is a property of semiconductor device physics and therefore not something you can do anything about.


* - 2 points to anyone who recognizes that classic quote

With regards to the short circuit , what we have experienced is not failures as most industrial IGBTs are short circuit rated for about 10us, less with the newer ones. What we have experienced are oscillations when we try to turn them off, and we think that the kirk effect is playing a role. The way I see it, if I can better understand the nuances I might design the drive in a way where it negates and issues.
 

Offline T3sl4co1l

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Re: Book for Gate Drive design and IGBTs
« Reply #3 on: July 25, 2019, 10:15:42 pm »
I'm not aware of any mechanism where the Kirk effect, by itself, can become active (oscillatory), rather than passive (dissipative, slowing).

More likely you've had dV/dt or EMI causing feedback in the driver?  Like, one discrete driver I tested, I saw this:


Inverter output voltage (inductive load, distinctive step due to diode to IGBT conduction)


Zoom on the falling edge. Very bouncy. Not due to inverter strays!


A different configuration, I don't remember what; triggered by coupling between drivers, maybe?

I changed to a more conventional architecture, with better isolators (SFH6345), problem gone.

Incidentally, I've always used desat detectors in my circuits, and have burned two handfuls of transistors my entire career.  One of those being a quad IGBT module, which is kind of unfair compared to the size of hands, mind.

Regarding short circuit behavior, one test we did was with one of those quad modules (1200V 300A per transistor, I think?), where we observed a peak up to 6kA or so, with successful turn-off and no damage.  Those modules were EOL at the time already; they handled this just fine.  I would be shocked if any IGBTs being made today suffer from turn-off problems.  (Hm, at least those in the 1200V range.  I could see medium-voltage parts managing to be harder to use, but don't know offhand.)


That said, the default desaturation threshold in many commercial IGBT gate driver ICs is around 7V which is almost always too high to save the IGBT when it is triggered; knocking a couple volts off that and setting the gate voltage when on to around 12-13V, instead of 15V, can improve the odds of surviving a hard short greatly (for NPT IGBTs, anyway; all bets are off with PT types). 

Irrelevant.  It takes roughly another three nanoseconds for Vce to rise from 7V to 15V, once the desat current is reached.

High desat thresholds are handy for systems integrating MOSFETs and IGBTs as assembly options; we also did that, where we used IGBTs for a low frequency power supply and MOSFETs for a high frequency supply.  The 900V MOSFETs available at the time had a generous Vds(sat), necessitating a desat threshold something like 50V.  (Desat isn't always employed, or suggested, for MOSFETs, but it works just the same, and prevented short-circuit failures in the system quite well.)

P.S.  I picked the wrong day to stop sniffing rosin fumes.

Tim
« Last Edit: July 25, 2019, 10:19:08 pm by T3sl4co1l »
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Offline MagicSmoker

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Re: Book for Gate Drive design and IGBTs
« Reply #4 on: July 25, 2019, 10:45:49 pm »
I'm not aware of any mechanism where the Kirk effect, by itself, can become active (oscillatory), rather than passive (dissipative, slowing).

I really only had the vaguest recollection that Kirk effect had something to do with bipolar devices, much less recall what it actually was, but a quick search refreshed my glue-addled memory. Basically, it is a massive increase in the time it takes charge carriers to transit the die at high current densities, and so it seems plausible that if the current reached into the zone where Kirk effect reared its ugly head that that could cause the on state voltage to increase which could cause current to drop which could reduce the Kirk effect causing current to once again increase, etc., and so on. But, again, this is more physics than engineering, per se.

Irrelevant.  It takes roughly another three nanoseconds for Vce to rise from 7V to 15V, once the desat current is reached.

I suspect you are assuming desaturation as a result of a cross-conduction type of failure, rather than a short in an external load (e.g., a motor or the primary of a transformer whose secondary is shorted)?

P.S.  I picked the wrong day to stop sniffing rosin fumes.

2 Points!!!  :clap:

 

Offline T3sl4co1l

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Re: Book for Gate Drive design and IGBTs
« Reply #5 on: July 25, 2019, 10:49:51 pm »
I suspect you are assuming desaturation as a result of a cross-conduction type of failure, rather than a short in an external load (e.g., a motor or the primary of a transformer whose secondary is shorted)?

Either one.  I mean, the exact rate of rise in Vce depends on the V(I) curve and the fault inductance (so, dI/dt), so a more distant short may not actually go from 7 to 15V in 3ns.  But in that case, this more modest fault condition will be managed by normal operation of the current mode controller, long before reaching desat magnitudes, so I don't see that it's anything to be concerned about. :-+

A typical design scheme is to have desat protection very close in (perhaps on the gate driver itself, with a feedback signal to halt the controller), then a current transformer (to measure load current) for normal feedback (control limiting/regulation/operation), with an overcurrent threshold so that if the controller can't handle it, it again halts.  (The desat signals can be wired-OR as a single fault signal, or individually latched to indicate possible service targets.)

Tim
« Last Edit: July 25, 2019, 10:56:15 pm by T3sl4co1l »
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Offline Phoenix

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Re: Book for Gate Drive design and IGBTs
« Reply #6 on: July 25, 2019, 11:18:57 pm »
I don't think you're going to find text books on the Kirk effect problem (short circuit robustness) considering it appears to be a more recent area of study. It also might not be a day to day problem, depending on your voltage/power levels, IGBT construction etc. I'd suggest trying IEEEXplore and IGBT manufacturer app notes for this level of detail.

This 2017 paper is a pretty good read on the topic https://vbn.aau.dk/ws/portalfiles/portal/281797878/2017_Reigosa_TPEL.pdf They conclude that the amplifying gate voltage oscillation during short circuit is caused by a parametric oscillator formed by the gate inductance and the Miller/gate capacitance. Where the capacitance varies as the electric field peak transitions across the device (apparently part of the Kirk effect).

This is new to me and I'm working in power electronics; did they even try to teach me Kirk effect at uni?
 

Offline bigamps

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Re: Book for Gate Drive design and IGBTs
« Reply #7 on: July 26, 2019, 04:05:42 am »
Like everyone else suggested, IEEE and app notes (such as Semikron's for high power) are your friends.
And you probably know this one book by formerly Infineon's Andreas Volke and Michael Hornkamp, although more focused on high power IGBTs:

https://www.igbtmodulesbook.com/

Enviado desde mi Aquaris X5 mediante Tapatalk

 

Offline Glenn0010Topic starter

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Re: Book for Gate Drive design and IGBTs
« Reply #8 on: July 26, 2019, 06:59:13 am »
Like everyone else suggested, IEEE and app notes (such as Semikron's for high power) are your friends.
And you probably know this one book by formerly Infineon's Andreas Volke and Michael Hornkamp, although more focused on high power IGBTs:

https://www.igbtmodulesbook.com/

Enviado desde mi Aquaris X5 mediante Tapatalk

Thanks all for the suggestions. I thought what I'm after might be a bit too specialised to find a book about it. I have been reading papers and application notes as I go. Application notes in general have bee really help full.

I did not actually know about that book, I'll try to get my hands on one!

Cheers
 

Offline MasterBuilder

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Re: Book for Gate Drive design and IGBTs
« Reply #9 on: July 26, 2019, 07:43:38 am »
I have found these resources very useful for my IGBT driver design needs.

Semikron application manual
https://www.semikron.com/service-support/application-manual.html

Also have a look here:
Bodos Power magazine
https://www.bodospower.com/default.aspx

If you want to go further, I would suggest searching for Academic papers on the subject.
 

Offline MagicSmoker

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Re: Book for Gate Drive design and IGBTs
« Reply #10 on: July 26, 2019, 05:11:47 pm »
I suspect you are assuming desaturation as a result of a cross-conduction type of failure, rather than a short in an external load (e.g., a motor or the primary of a transformer whose secondary is shorted)?

Either one.  I mean, the exact rate of rise in Vce depends on the V(I) curve and the fault inductance (so, dI/dt), so a more distant short may not actually go from 7 to 15V in 3ns.

I think you missed my point: the Vce[sat] for most IGBTs that are rated at 1700V or less is in the range of 1.2V to 3.0V, and it increases with Ic as one would expect for a bipolar device (that is, 60-120mV/decade of current, plus a bit more due to the various resistances), so triggering desat at 7V is needlessly abusive. For example, even if Vce[sat] is 3.0V at rated Ic, it will likely only increase to about 3.5V - 4V at 2x Ic, and maybe 4V - 4.5V at 3x Ic, etc., but once desaturation occurs - which could be anywhere from 2x to 6x rated Ic, depending on the precise construction of the die - Vce will shoot up rapidly, to the point that the device will act more like a constant current source. Triggering desaturation protection a couple volts lower than the standard 7V threshold isn't so much to grant the protection circuit more time, it is to reduce the peak power experienced by the switch. Besides, to make a reliable desaturation protection circuit you have to ignore Vce when the gate is first brought high for 200ns - 1us, anyway, to avoid false triggering.

That said, if the fault is cross-conduction of a half-bridge directly fed from a dc link capacitor then there is almost no hope of protecting the IGBTs, even if the Vce threshold is lowered to 5V, as fault current might very well zoom up to the desaturation-limited value even during the blanking time for the desat detection circuit, and then it's more a case of, "Abandon Hope, All Ye Who Enter," etc.

But in that case, this more modest fault condition will be managed by normal operation of the current mode controller, long before reaching desat magnitudes, so I don't see that it's anything to be concerned about.

That assumes this is a power supply employing current-mode control, when it could be a power supply using voltage-mode control with cycle-by-cycle overcurrent protection, or a PFC stage using average current mode control, or a motor drive also only using cycle-by-cycle current limiting, or a motor driving using average current mode control and relying on desaturation detection as well as a peak-detector on a Hall-effect transducer for overcurrent protection, a UPS running a fixed PWM waveform without a control loop at all - you may shudder at this kind of sloppy design but I've actually seen it in a commercial product, etc.


A typical design scheme is to have desat protection very close in (perhaps on the gate driver itself, with a feedback signal to halt the controller), then a current transformer (to measure load current) for normal feedback (control limiting/regulation/operation), with an overcurrent threshold so that if the controller can't handle it, it again halts.  (The desat signals can be wired-OR as a single fault signal, or individually latched to indicate possible service targets.)

Yep, this is a good plan of attack if your budget allows such a braces and suspenders approach (substitute a Hall-effect transducer for current transformer, where appropriate).

 

Offline T3sl4co1l

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Re: Book for Gate Drive design and IGBTs
« Reply #11 on: July 26, 2019, 06:37:25 pm »
I think you missed my point: the Vce[sat] for most IGBTs that are rated at 1700V or less is in the range of 1.2V to 3.0V, and it increases with Ic as one would expect for a bipolar device (that is, 60-120mV/decade of current, plus a bit more due to the various resistances), so triggering desat at 7V is needlessly abusive. For example, even if Vce[sat] is 3.0V at rated Ic, it will likely only increase to about 3.5V - 4V at 2x Ic, and maybe 4V - 4.5V at 3x Ic, etc., but once desaturation occurs - which could be anywhere from 2x to 6x rated Ic, depending on the precise construction of the die - Vce will shoot up rapidly, to the point that the device will act more like a constant current source. Triggering desaturation protection a couple volts lower than the standard 7V threshold isn't so much to grant the protection circuit more time, it is to reduce the peak power experienced by the switch. Besides, to make a reliable desaturation protection circuit you have to ignore Vce when the gate is first brought high for 200ns - 1us, anyway, to avoid false triggering.

If it's rated for 10us of short circuit, what's the difference?  It still survives.

Lower and lower thresholds are more sensitive to errors, and prone to false triggering; and you want to avoid blanking and filtering schemes where possible.


Quote
That said, if the fault is cross-conduction of a half-bridge directly fed from a dc link capacitor then there is almost no hope of protecting the IGBTs, even if the Vce threshold is lowered to 5V, as fault current might very well zoom up to the desaturation-limited value even during the blanking time for the desat detection circuit, and then it's more a case of, "Abandon Hope, All Ye Who Enter," etc.

Whose IGBTs are hopeless?


Quote
That assumes this is a power supply employing current-mode control, when it could be a power supply using voltage-mode control with cycle-by-cycle overcurrent protection, or a PFC stage using average current mode control, or a motor drive also only using cycle-by-cycle current limiting, or a motor driving using average current mode control and relying on desaturation detection as well as a peak-detector on a Hall-effect transducer for overcurrent protection, a UPS running a fixed PWM waveform without a control loop at all - you may shudder at this kind of sloppy design but I've actually seen it in a commercial product, etc.

The predecessors to the designs I was working on, were basically wide open loop, old school, verbose logic designs.  They didn't even use oscillators, they slapped together a bunch of monostables to do it.  Lots of CD4000 or 74AC logic, on the premise that the higher voltage, or lower output impedance, provides noise immunity.  Lots of opamps, for reasons I never quite understood (only a couple are really needed, for a full analog+logic design of that capability).  The old guard laughed at our choice of FPGA with its 1.1V core; but go figure, they didn't know anything about EMC, they just cookbooked everything.

Point being, the gate drivers similarly were just that, a transformer to supply DC power, an opto to couple signal, and an IRF(9)540 H-bridge to drive the gate to +/-15V.  No desat protection (would be hard to implement with that H bridge output, anyway), no current sensing, aside from the one current transformer (common to all inverters in parallel) for feedback (phase and amplitude, this was a resonant system).  Controller terribly slow, dominant pole compensated, you could watch the dials as it started up (settling time in the fractional seconds).

So, needless to say, they burned a lot of transistors on those designs.  But service is so expensive that they really don't care about transistors as such, and operation is usually so consistent (industrial process equipment) that they can get years of continuous operation despite the dumb design.

There was also the even older generation of SCR inverter units, which I had nothing to do with, but saw them come in for service from time to time.  Think the controls were even more limited on those, but again they were only used on very stable loads so if it starts up once, and stops once, successfully, who cares...


Quote
Yep, this is a good plan of attack if your budget allows such a braces and suspenders approach (substitute a Hall-effect transducer for current transformer, where appropriate).

Yes, which since we're talking $200 IGBTs here, the added cost is quite small, and the savings (to the customer) in service calls is huge.

Tim
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Offline Glenn0010Topic starter

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Re: Book for Gate Drive design and IGBTs
« Reply #12 on: July 30, 2019, 07:53:11 am »
I've started going through all of the materials you guys linked, and I'm going to be busy for a while! I've also been brushing up on the FET chapter of the Art of electronics (I am switching IGBTs but they are similar). It should help jog my memory back with anything that I may have forgotten
 

Offline MagicSmoker

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Re: Book for Gate Drive design and IGBTs
« Reply #13 on: July 30, 2019, 01:50:02 pm »
If it's rated for 10us of short circuit, what's the difference?  It still survives.

Lower and lower thresholds are more sensitive to errors, and prone to false triggering; and you want to avoid blanking and filtering schemes where possible.

It took me a couple days to get around to doing this, but I excerpted the relevant portions from a state-of-the-art IGBT datasheet to illustrate my points. Basically, if Vge is 15V and desat threshold is 7V then short circuit current for this "50A" rated IGBT is so far off the scale who knows what it will end up at (though, from experience, trench gate NPT IGBTs typically desaturate at 6x rated Ic). If the desat threshold is dropped to 5V and Vge is also lowered to 13V then short-circuit current will top out around 180A, just based on linear extrapolation of the graph.

This puts far less energy into any stray inductances which will complain loudly during the turn-off process, greatly reduces the peak power dissipation in the IGBT, and turns a lifetime-reducing event into one that is barely noticeable, all at the cost of about 0.1-0.2V of additional voltage drop during normal operation at rated Ic. I'm not even mentioning any theoretical increase in false triggering from lowering the desat threshold to 5V from 7V because it simply doesn't exist (not unless your layout is so awful that 5V logic won't work reliably, either).

In contrast, not inhibiting the desat detection comparator for at least as long as the sum of the turn-on delay and rise times will result in false triggering - you simply can't avoid this blanking time, though in this case it's relatively short (<100ns at 175C, though note that only typical values are given...).

 

Offline max_torque

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Re: Book for Gate Drive design and IGBTs
« Reply #14 on: July 30, 2019, 07:31:32 pm »
Given that you work for a drives company, with i suspect a long history of making, er, drives, then the best thing you can do is to raid the archives i suspect, and find every gate driver circuit ever used by your company in a product.  Go talk to the service dept as well, and find out which drives had good reliability, and those that didn't, and find out what the primary in-service failures were caused by!

IMO, that will be worth far more than getting bogged down in possibly completely irrelevant theory!
 

Offline T3sl4co1l

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Re: Book for Gate Drive design and IGBTs
« Reply #15 on: July 30, 2019, 07:41:27 pm »
Yeah, running a slightly lower Vge(on) can help with that.  15V may not be necessary for operation, and 10-13V probably won't increase dissipation enough to matter.

Energy in stray inductances doesn't matter, as far as dissipation.  It'll amount to a few hundred nanoseconds of additional short-circuit dissipation, negligible compared to the event itself (which is already several microseconds due to intentional comparator filtering and delay).

Overvoltage due to strays, can be a problem; for this reason, many gate drivers (and now we come back on topic, yay!) offer a slower turn-off under desat/fault condition.  This trades peak voltage for more dissipation, and again, if we're already well under the limit, we aren't costing much reliability by holding out a few hundred nanoseconds longer.

So that's basically the last option for OP to consider: slow turn-off under fault condition.  Vge(on), Vge(off), Ig(pk) or equivalent driver output resistance, desat detection, and faulting turn-off, should be the full set of features to consider.  (You can always do more, like use a high speed serial link to communicate timing and status; you could put an ADC up there to monitor local temperatures, sample gate or drain voltages or currents, etc., but that would be a bit over-the-top for most anything.)

Tim
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