Ground plane vs. top ground pour (for > 2 layers)

[jmw]

Let's talk about grounding: if you've got an internal plane layer for ground, what good is it to pour copper near everywhere for ground on the top layer? Compare the following three styles of ground connections:


a) connect pad to top layer ground pour, with few number of ground vias. This doesn't take advantage of having an internal ground plane, but it seems it would be an alternative to having a split ground plane if you want to isolate return paths for certain digital and analog components.


b) short-length trace from pad to via to ground plane, no generous top layer ground pour. This seems the easiest to understand: every ground pad gets dropped to the common ground plane. Other than traces and other net pours, there isn't going to be much copper on the top of the board following this style.


c) pour ground generously on the top layer AND drop a via close to pads. Unless you also need a CPWG on the board, I'm unsure what advantage this offers over (b) - it just electrically staples together your surface and internal ground planes in many places. Is this the equivalent of wearing a belt and suspenders?

What style do you use and why? Are there other, non-electrical, reasons to pick one (e.g. I have heard that having varying levels of copper density affects ease of imaging)?

[T3sl4co1l]

Short trace to via.

Where low inductance bypassing is called for, two vias can be used, flanking the pad, and connected with trace about the same width as the via pad.

I almost never bother to pour routing layers.  The advantage is slight, and the cost is huge -- it's such a mess stitching it together, resolving vias across all 4+ layers!

How much stitching is actually necessary -- or how much ground fill is actually necessary -- is a matter open to argument and depends on the application.  General applications don't need the slight improvement in shielding (RFI related), and the trace width for controlled impedance isn't affected very much (CPW, that is).  The reduced coupling between parallel routed traces (interleaved with grounds), may be a greater value, but again isn't at all necessary in the most common case, digital signaling.

Tim

[Neilm]

2nd the short trace to a via.

Also, I would not split the 0 V plane into analogue and digital just because "that was how we did it in the 70's" or what it says on an apps note. I have seen too many products fail EMC immunity tests purely due to that to ever recommend it. That is not to say there are not situations where it may be benificial - just don't do it because you think (or someone says) it is a good idea.

Also - if you do copper pour the top layer it has to be reasonably well stiched to 0 V. I have seen recommentations of vias every 10 mm, but I personally think that could degrade the 0 V plane, you are basically punching holes in it with each via.

Neil

[pigrew]

Not that I'm an expert, but there are a few other reasons to have a pour:

• Better thermal conductivity, so your board can act as a better heatsink.
• Less etchant used. During etch, not as much copper has to be removed, so the etchant will last longer.
• Helps the metal fill to be relatively constant throughout all the layers, which reduces the risk of the board warping during bakes/soldering.
• Makes prototype-rework slightly easier. Scratch off the solder mask if you need a short connection to a ground, or you can cut a new pad into the copper if you need an isolated pad.
  

Personally, I do a GND fill since I don't see any downsides (other than slightly longer compute time). I try to put a via next to every GND pad (and use thermal relief).

[SiliconWizard]

Yeah, I've also made a habit of pouring the outter layers (top & bottom), but usually not internal signal layers (for > 4 layers).

And yes, it helps when you have to fix stuff on prototypes. You always have close access to GND wherever you need it.