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Boost Converter PCB Layout

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Electr0nicus:
Hi

I currently designing a battery operated device. 8) It runs from a 1s3p Li-ION 18650 battery pack. To generate the 12V System rail, I use a LTC3786 Boost Converter. I spent the last few days with shuffling around the components and finding an optimal layout. So I came up with the following layout, which in my opinion, is very good. But still I'm not 100% confident if it is really as good as I think. So maybe one of you more experienced guys can have a look and suggest things which can be made better.





Kind regards
Gregor

sacherjj:
You have a very copper heavy layer (which is good).  There are components that most likely need better thermal isolation.  An example of this is CP2.  Good thermal isolation on one pad, and none on the other.  Same with CP1.  Rsense has no thermal isolation, which may or may not be fine.

None of these would be a problem with hand assembly, however I would not be surprised to see a large number of CP1 and CP2 tombstone with reflow.  The thermal isolated pads will cool down faster than full copper pads.  This can make the cooling solder lift the component out of the still molten full copper pad.

AndyC_772:
The voltage developed across RSNS is going to be small, and any noise picked up on top of it will affect the stability of your regulator. Is it not possible to flip the overall layout so that RSNS is next to the controller?

nctnico:
I didn't read the datasheet but there is a voltage feedback loop so I think Rsense is there to limit the current through the MOSFET.

Then again I would try to put CP1, L1 and BMOS together as close as possible. A lot of current is circulating in those parts.

Electr0nicus:

--- Quote from: sacherjj on January 13, 2014, 09:51:25 pm ---You have a very copper heavy layer (which is good).  There are components that most likely need better thermal isolation.  An example of this is CP2.  Good thermal isolation on one pad, and none on the other.  Same with CP1.  Rsense has no thermal isolation, which may or may not be fine.

None of these would be a problem with hand assembly, however I would not be surprised to see a large number of CP1 and CP2 tombstone with reflow.  The thermal isolated pads will cool down faster than full copper pads.  This can make the cooling solder lift the component out of the still molten full copper pad.

--- End quote ---

That will be indeed a problem with reflow soldering. But how will thermals affect the high current properties of the components, as you literally reduce the "trace" width on every component pin? Will it be tolerable if all pads have no thermal isolations, as they will approximately cool down equally fast?
Although this problem doesn't bite me yet, because I don't have the intention to produce more than 10 PCBs any time soon :)


--- Quote from: AndyC_772 on January 13, 2014, 10:15:30 pm ---The voltage developed across RSNS is going to be small, and any noise picked up on top of it will affect the stability of your regulator. Is it not possible to flip the overall layout so that RSNS is next to the controller?

--- End quote ---

Yes I've tried that. It shortens the RSNS leads but makes many other things worse. As your Mosfet gate drive signals getting longer and will be routed under the inductor and switching node, also the feedback trace will have to be routed directly on the bottom layer from  VOUT to the regulator on top. And that feedback trace I consider much more sensitive than the RSNS traces. In my current layout it's very short and on the "quiet" part of the PCB.  Also the chip will be much nearer to the inductor. The sense lines themselves are low impedant and the loop area is very small, so interference should be minimized. The highest di/dt occours around the TMOS, BMOS and the output caps. The input caps have a relatively low di/dt.


--- Quote from: nctnico on January 13, 2014, 10:43:15 pm ---I didn't read the datasheet but there is a voltage feedback loop so I think Rsense is there to limit the current through the MOSFET.

Then again I would try to put CP1, L1 and BMOS together as close as possible. A lot of current is circulating in those parts.

--- End quote ---

I agree with your first statement, but disagree with your second one. It is a boost regulator. So the currents trough CP1 and L are really slow rising, as the inductor slowly charges up, the current rises. The really high currents flow when the inductor is switched off and the energy has to be transfered to the output caps. In the datasheet they write:


--- Quote ---Put the bottom N-channel MOSFET MBOT and the top
N-channel MOSFET MTOP in one compact area with
COUT .
--- End quote ---

http://cds.linear.com/docs/en/datasheet/3786fa.pdf

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