How to approximate SOA of a clamping/ESD structure?

[MiDi]

How could one approximate the minimum input series resistance so that a component can withstand a sudden discharge from a capacitor through the clamping/ESD structure?

Example:
Protect an opamp with capacitors on its inputs in case of a sudden short of the supply rails.

From datasheet absolute maximum and ESD ratings:
input DC current: 10mA
HBM: 4kV
CDM: 1kV


It would be safe to keep input currents below 10mA, but the resulting series resistor is higher in value than it needs to be.
Adding external protection would be an option, but want to exclude this here.

[Kleinstein]

The data-sheets often don't give seprate specs for maximum pulse current and more DC like current limits in the absolute limits. So techically there is no extra safe range beyond the specs and one is a more gray area. So on your own risk and how sturdy a chips is may change in future batches.

With chips there can be different processes that can be limiting, especially thermal of the chip, the bond wire and triggering of latch up.
The thermal limit and the bond wires  can tolerate more for a shorter time scale. For the latchup limit, there is only very little to gain for short pulses (the parasitic transistors are usually not super fast and may need a few µs to build up base carriers). The latch up limit however usually gets better with lower or no supply.  If the supply is weak, some chips can even survive a latch up.

For limiting the current, at least for the very shart part and relative high currents the inductance can also help.
The usual way to protect inputs is to have multiple layers, not just the chip internal diode. So most of the ESD pulse flows through other diodes or is lengthend by capacitors. 2 stage clamping can be quite a bit more effective than just 1 stage.

[T3sl4co1l]

Assuming the ESD structure activates in the same way (a supply-shorting mechanism seems to imply we're talking clamp diodes here), you could reproduce the ESD waveform, scaled appropriately.  4kV HBM implies 2.67A peak and a time constant of 0.15us.  So, set Rs and Cmax accordingly.

For C higher than the scaled value, you can't guarantee the same pulse duration, and so more charge will be absorbed, which might activate other mechanisms (e.g. electromigration).  Energy or power may be above their respective curves as well, but you don't know those curves, how they scale with time that is, so the next safest plan is to honor the DC current limit.

So, from available data that would be something like a limit of 2.67A for some 10s of ns, dropping along some slope or curve to the 10mA DC figure.  Almost certainly, this curve/slope can be shallower than the discharge tail of the HBM event, but taking that as a minimum limit, it drops to 10mA after about 800ns, so that seems a safe assumption.

Example: so, whereas HBM is 100pF + 1500R at 4kV, you could presumably do, say, 1nF at 400V and 150R.  If supply was 15V, maybe even as much as 27nF with 5.6R.  Mind, the pin's internal resistance will start to dominate in this regime, dissipating more out of the total energy (but, 27nF @ 15V is also much less energy than 100pF @ 4kV, so that's not necessarily a problem), and also affecting the time constant -- that is to say, we can't assume the pin is an ideal ground down here, whereas if it's dropping, you know, 30V or something, that's negligible out of 4kV.

The real problem, then, is trying to infer scaling laws from limited data, and extrapolating across two decades of scale!

In any case, the given problem is trivially avoided with external clamp diodes (which will handle much more current at lower voltage drop), so that's not a big deal.  Supply filtering may be relevant as well (assuming the shorting event happens elsewhere; and if it does happen locally, it probably means something local has failed worse to begin with?).

Tim