You start to get concerned up there (100s MHz), but for most MCU stuff there really isn't anything better than simply vias to the plane. The MCU pins can't see the cap on the far side, it's shielded by both planes; there's no mutual inductance or anything going on there. So the situation can't be any worse, if it's acceptable in the first place to put it somewhere other than directly adjacent.
What's more, because the plane is such a low impedance, it acts as a nearly ideal connection between everything tied into it. It doesn't really matter where you put the bypass caps, or how many there are. You might scatter a few around the board, instead of meticulously bypassing every damned pin (which if you follow religiously, tends to make things worse anyway*..). No, it doesn't much matter what the loads are, they can all share each others' bypasses; as long as they aren't synchronized, which, if you have that situation, by all means watch out, but a lot of applications are doing different things in different areas and it's perfectly fine.
*Namely, that having too many capacitors invites resonances between them (especially when values or sizes are tapered -- that's almost always advice to ignore), and the sheer component count causes congestion in routing actual useful signals. And if the process also greatly increases the number of vias around the chip in question, the swiss-cheese made of the planes makes the planes themselves perform worse!
Incidentally, higher clock frequencies aren't usually much of a burden, either. There simply isn't a short enough length between PCB and die to be able to maintain low supply impedance from PCB bypass alone. This is why high speed chips have onboard bypassing, either on an interposer board, stacked on top of the die, or part of the die layout itself (metal layers being interleaved, in exactly the same way, and for exactly the same purpose, as PCB planes). PCB pins get iffy above 100MHz or so.
Tim