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| Cable tester/TDR strange result |
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| magic:
capacitors ;) edit And by the way, I agree with tggzzz that your output resistors are suspiciously low. My measurements of SN74LVC2G14 indicated 8~9Ω of output resistance per pin while driving 200Ω load, tggzzz says 7Ω for 300Ω load. The exact value may vary with output current (FETs aren't exactly resistors) so do your own testing. Simply connect 50Ω load, override the circuit to output 3.3V permanently and measure the exact output voltage with a DMM. A slight mismatch may be the reason why the falling edge doesn't fall all the way to zero right away. You will probably find that the output voltage into proper termination also isn't exactly 50%. The initial overshoot and ringing could be improved by bringing the 100nF capacitor closer to the IC, but it seems you are already close to the limits of your chosen package here. |
| jmw:
The datasheet (https://www.ti.com/lit/ds/symlink/sn74lvc14a.pdf) lists V_OH = 2.3 V (min) at VCC = 3 V and I = 24 mA, and V_OL = 0.55 V (max) at same VCC and current levels, so that where I came up with (3 V - 2.3 V)/(24 mA) = 29.2 ohm and (0.55 V)/(24 mA) = 22.9 ohm. 4 x 180 ohm seems to be a good match, as in using a 50 ohm termination on the cable you have to look closely to discern a second jump. It's still probably tunable for that last 1-2%. Switching to 0402 for 100 nF to get it ever so closer to the IC is doable, as is going to 4 layers. I'll have to test out bodging bulk capacitance onto the board. OTOH, there's still the question if there's a categorically better LDO to use than NCP551. |
| tggzzz:
The VOH IOH type calculation is principally useful at "DC", i.e. when the transition has completed. Where purity of the transition is more important, the output resistance at other points is more important, and will be lower. The difference between the two will be minimised by using more gates, since each transistor will not have to be supplying the full current. Hence the best output resistance, which will have to be determined empirically, may depend on whether you are interested in a "short range" or "long range" TDR. Having fewer gates in a package shares the effects of package lead resistance/inductance across packages, and allows more capacitance to be placed near each gate. Those are good w.r.t. the edges, as is having a solid ground plane and power plane as close together as possible. |
| magic:
--- Quote from: jmw on January 20, 2020, 04:45:46 am ---The datasheet (https://www.ti.com/lit/ds/symlink/sn74lvc14a.pdf) lists V_OH = 2.3 V (min) at VCC = 3 V and I = 24 mA, and V_OL = 0.55 V (max) at same VCC and current levels, so that where I came up with (3 V - 2.3 V)/(24 mA) = 29.2 ohm and (0.55 V)/(24 mA) = 22.9 ohm. 4 x 180 ohm seems to be a good match, as in using a 50 ohm termination on the cable you have to look closely to discern a second jump. It's still probably tunable for that last 1-2%. --- End quote --- You are right in principle, but this is the worst case output resistance guaranteed over the entire -40~125°C temperature range at VCC=3.0V. It's going to be lower in practice, lower still if the device doesn't operate at temperature extremes and slightly lower at VCC=3.3V too. Sorry, no idea about fast LDOs. |
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