Can Bidirectional Level Translators drive 5v TTL Inputs?

[hal9001]

Can bidirectional level translators drive 5v TTL inputs? My concern isnt the voltage but the current requirements a TTL input pin needs.
For example the TXB0108 uses 4K ohms resistors to maintain a high or low but it has higher current to switch the pin at first. From datasheet

In a dc state, the output drivers of the TXB0108 can maintain a high or low,but are designed to be weak so that they can be overdriven by an external driver when data on the bus startsflowing the opposite direction. The output one-shots detect rising or falling edges on the A or B ports. During arising edge, the one-shot turns on the PMOS transistors (T1, T3) for a short duration, which speeds up the low-to-high transition. Similarly, during a falling edge, the one-shot turns on the NMOS transistors (T2, T4) for a shortduration, which speeds up the high-to-low transition. The typical output impedance during output transition is 70Ω at VCCO = 1.2 V to 1.8 V, 50 Ω at VCCO = 1.8 V to 3.3 V and 40 Ω at VCCO = 3.3 V to 5 V

With 4K ohms drive this means only 1.3 mA for 5v after a transition. Will this work to interface to 5v TTL inputs?

Thanks

[T3sl4co1l]

The TXB thingys are a trap for young players.  Use a level shifting buffer.

Tim

[ConKbot]

+1, just say no to the TXB series. Biggest smile on my face at work recently has been designing them out of a board, and scoping the nice smooth, ringing free SPI line from a unidirectional level shifter with a 20-30 ohm resistor on the output to get its output impedance close to what the trace should approximate, even with going across multiple connectors on the way. 2 SPI busses, 8 port shifter, nice small package, seemed great, at first. Ended up a mess of weird ringy, rising and falling edges, with multiple slopes as it switched from the one-shot to pull-up. When SPI was being weird, we never were sure if it was software being strange, or the hardware double clocking, etc...
Nevermind the amount of times I've had to help software devs with devboards attached together with a TXB on a breakout and big long ground leads that made the whole test setup even more spotty.

[MarkF]

+1, just say no to the TXB series. Biggest smile on my face at work recently has been designing them out of a board, and scoping the nice smooth, ringing free SPI line from a unidirectional level shifter
 . . .

Out of curiosity, exactly which part did you use (or have had the best success with)?

[ConKbot]

+1, just say no to the TXB series. Biggest smile on my face at work recently has been designing them out of a board, and scoping the nice smooth, ringing free SPI line from a unidirectional level shifter
 . . .

Out of curiosity, exactly which part did you use (or have had the best success with)?

Pretty much every level shifter Ive used hasnt been a problem, dual rail unidirectional, single rail unidirectional, etc. The NLSV4T244E was the one in this specific case, I was doing 1.8v-3.3v translation, so them only handling up to 4.5v on the supply rails wasnt much of a problem, and I had enough IO that them being 4 channels in the same direction wasnt a problem either. Havent used it but the NLSV4T3144Looks like it would be ideal for a single SPI bus channel. (That one has an absolute max VCC voltage limit of 5.5v, but I'd be I wouldnt be tempted to run it off of 5V given the recommended is only up to 3.6v, and there is no characterization for operation at 5v).

Be mindful of just how fast both of these are in a design though. That 24mA @3.3vcc output drive, and low propagation delay can put out some sharp edges that will start making things ring if you dont have something approximating a transmission line with good grounding. Not saying to go all in and get a controlled impedance board with 50 ohm lines, but getting the lines near 50 ohm, making provisions for ground currents to change layers when the signal changes layers, plenty of grounds in connectors, and the resistor on the output to get its output impedance closer to 50 ohm is what paid off for me. Even then the edges were so fast I'd consider increasing the resistor to slow them down since they were unnecessarily fast for 10 MHz SPI. Dont go stuffing your entire rising edge into your transmission line if you dont need to. I forget what the rule of thumb is (rising edge length in transmission line / x) for when you can get away with whatever your want vs having to consider transmission line effects more seriously.  But I'd rather have the choice of my rising edge with a resistor than to be stuck with something.  Dont forget good decoupling too, even with the resistor making them closer to 50 ohms per channel, thats a 12.5 ohm transient load if all 4 channels transition at the same time.

Ive also used the SN74LV1T86 for a go-to wide and unknown input range conversion. Running off a 2.5V rail, I can feed anything from ~1.5V to 5V into it, (mind your logic low levels for feeding it 3.3 and 5V logic of course). And with it being an XOR, a configurable pull up or pull down on the other input give you the option of flipping the polarity.

[T3sl4co1l]

Yeah, for more generic application, 74HC, HCT, LV, LVC, AHC are likely choices (and whatever TinyLogic equivalents are to them).  Check the datasheets/family databooks: they're each suitable for different purposes, varying in voltage range, input protection (HC(T) has double clamp diodes, LV(C) has GND clamp and zener/snapback), speed (LVC faster than HC), output enable (LVC I think all has a no-bus-loading feature when unpowered?), and available functions (there's a 74(LS)06 with 30V open-collector outputs, but no HC; there's a 74HC05 with open-drain outputs and clamp diodes to supply, but no 74LVC05, however there is a 74LVC06 without clamp diodes but only a 6.5V voltage range; etc.).

The only annoyance with SPI is, you often need 3/1 forward/backward, so you need two different devices to translate, or four single channel devices.  Sometimes it can be convenient to use something simple like divider resistors, a diode gate, or a single transistor for the odd one out.

The above notes about signal quality and transmission lines are spot on.  These signals are fast, particularly from the faster logic families, and from most CMOS ASICs (MCUs, etc.).  If you have poor grounding, poor signal routing, poor cable allocation (e.g. not using ribbon cable with every other grounded, or using multiconductor cable with random assignments or few grounds), you will get spooky, sequence-dependent behavior.  Maybe it fails on a single transaction, maybe it's good for a hundred, or a thousand, maybe it only works when a certain bit pattern is emitted, or when another device is communicating at the same time (introducing coincident noise across the board, coupled through supplies or nearby traces).

I've seen it happen just on solderless breadboard, with an ordinary ATMEGA32 and 6" jumpers.  Slip a ferrite bead over 'em, no problem.

I will add the modification, traces aren't usually 50 ohms; 70 to 100 is more typical, especially on 2-layer board (pour ground plane both sides and stitch with plenty of GND vias!).  Narrower traces have higher impedances.  To see what, use a calculator, and choose the appropriate geometry: microstrip most common for 4-layer boards; 2-layer with ground pours both sides is coplanar waveguide with ground (CPWG).

The exact impedance hardly matters, just so long as it's modestly well terminated -- say, within 30% of the source and/or load resistance.  (Same as the 30-70% of supply that CMOS input thresholds typically have.)  CMOS output pins are usually on the lower side (30-70 ohms), so a little resistance (22-47 ohms) in series with the pin driver, located at the driving pin, can be a great help.  And you can always use higher resistances, or ferrite beads (with Z @ 100MHz being comparable -- typically 100-500 ohms), to get slower edges (more filtering), when speed isn't critical.

It's possible to design multi-master buses and other topologies as well, though I won't go into detail at this time.  Just to note that, when you have a pin driving traces going in multiple directions, or traces teeing off, the impedance is different, and those structural changes need circuit changes to support them (and may also require a reduction in bandwidth, or a change in transmitter/receiver type).

Tim

[ConKbot]

I will add the modification, traces aren't usually 50 ohms; 70 to 100 is more typical, especially on 2-layer board (pour ground plane both sides and stitch with plenty of GND vias!).  Narrower traces have higher impedances.  To see what, use a calculator, and choose the appropriate geometry: microstrip most common for 4-layer boards; 2-layer with ground pours both sides is coplanar waveguide with ground (CPWG).

Yep, this is true. I was working on a board with a bunch of fine pitch 90/100 ohm differential signals, so I already had thin dielectrics in the stackup for other reasons.  More reasonable stackups will be higher impedance for usual line widths.

[hal9001]

Thanks all! It looks like unidirectional is safer than the TXB.

Out of interest, if board space and cost doesnt matter, is there a reliable scheme to sense direction of a bus using external electronics to control a level shifter that has a direction pin?
For example using a comparator or CPLD to detect changes? This can be easy if there is a control pin to tap into but I wonder if it can be done for an arbitrary signal..

[T3sl4co1l]

In an impedance matched environment, you use a directional bridge.  For typical CMOS, the load is far from matched (at all frequencies) and at best, you have to come up with all sorts of hacks -- like the TXB has -- to manage it.

I mean, knowing that one side changes and the other doesn't (they aren't connected through, the interface has complete control of transmission) is a pretty clear sign that one side is transmitting.  But how do you know if the other side has asserted, and it just happens to be at the same value?

If you could allow the line to float around or load down a little, you could check the margins, i.e. how far from VDD/VSS it is: if it reads a hard say <10% or >90%, it must be asserted, whereas if we drive it weakly at 20/80% it's passive; but this has weak drive capability (we're increasing output resistance) so affects fanout and speed, probably wastes quiescent current (the margins are easiest created with resistor dividers), and reduces noise margin (against the typically 30-70% threshold range of CMOS, however some are 20-80% so we really don't have much to work with here).

And really, this is all just a bastard attempt at the first thing I mentioned, a directional bridge: if we have known source and load resistances, then we can simply take the ratios of voltage and current from each side, and forward that condition to the other side at its respective voltage level.  The fact that source and load are matched, means we don't even care about output-driving-output conditions; but this is a very analog sort of signal and not very useful onboard, as logic 1/0 levels are 25 and 75% (+/- some margin), requiring more complicated receivers than traditional CMOS inputs; and it has a fanout of 1.

Ed: It's definitely something that's been done -- analog phone is built this way, using transformers to couple to the handset mic and speaker.  Looks like old fashioned 10BASE2 used a similar mechanism to detect collisions on a coax bus, though only during active pulses, as the inactive state is undriven (data are Manchester encoded, i.e. constantly toggling up and down, the order being determined by bit value; so this probably does alright).  CAN and I2C similarly detect collisions on an open-collector style bus, so can only detect anything out of the ordinary when an undriven state was expected but the line was pulled low by something else.  Not sure offhand what interfaces detect collisions in both high and low states.

Tim