Small signal DC unity gain buffer, avoiding overshoot

[stephanm]

When experimenting, I sometimes want to drive a stable DC voltage into some point of my circuit. Use cases are feeding ADCs or DACs with a reference voltage, changing biasing points in a circuit (by superimposing an external voltage on a node in a circuit throgh a resistor), supplying a VCO with a tuning voltage, simulating a voltage from a sensor on a circuit's input, etc.

An utility instrument for doing the above would be like a PSU, but with a low current output. For the overall construction, I was thinking of an ADC followed by an output stage, basically an unity gain voltage buffer. Leaving aside the voltage generator (ADC) part, I'd see the following requirements for the unity gain voltage buffer circuit:

- DC output voltage: -10V to +10V
- Offset voltage less than +/- 100uV
- No need for speed: settling times in the order of many 10's of milliseconds are OK
- Max output current for maintaining regulation: 10mA (sourcing and sinking)
- Max short circuit output current: max. 20mA (ideally for shorts to any external DC voltage between -30V and +30V)
- Stable with capacitive loads from 1pF to 50uF
- High impedance input (the driver in front of the output stage will likely be an op amp)
- Low AC output impedance
- No output capacitor
- As little overshoot/undershoot as possible, see below

I was simulating a few circuits in the past, and while I am not seeing an issue with most of the above requirements, I have some difficulties with the last point. My goal would be to have an output stage with only little under-/overshoot when the input voltage changes, but also when it recovers from short circuit or overload conditions. With "little", I mean less than, say, 200mV, i.e. low enough to not turn on ESD diodes in ICs. In a similar way, the requirement of having no output capacitor is meant to protect sensitive circuitry from seeing current spikes from my DC voltage generator when it's output capacitor discharges into the target circuit.

After having spent some many hours on this topic already, I'm no longer sure whether I have experimented with the wrong circuit topologies so far, or if I'm just overdoing my specs. Any comments or help will be appreciated.

From my experiments so far (read: simulations), the problem with overshoot/undershoot on recovery from shorts on the output can be boiled down to a situation that can already be seen in the circuit shown in the image. The resistors and diodes are meant for protecting op amp U1 in case of overload conditions. Note that it's clear to me that this circuit can have stability issues with capacitive loads and some DC issues as well. Also, don't take the component values too seriously, this circuit is just meant for discussion.

Suppose a load sinking 10mA is connected to DC_OUT while DC_IN=3V. Due to R1, the op amp's output voltage will be 4V, in order to compensate the 1V drop across R1. When the load current suddenly drops, for example to 1uA, DC_OUT will be at 4V until the op amp regulates it's output voltage back to DC_IN + 1uA*100 Ohms. So using the component values shown above, with this change of the load on DC_OUT the output will overshoot by 1V, more than what I wanted to have. Reducing R1 will help to lower the overshoot, but the price is a loss of protection when DC_OUT gets accidentially connected to some voltage beyond U1's supply voltages. Also, with a fast op amp for U1, the duration of the overshoot can be reduced, but what should be an upper limit in terms of time to play safe with sensitive circuitry connected to DC_OUT?

Another use case for such an output stage circuit would be buffering a precision voltage reference, such as an LM399. Here, the tradeoff I see is that the output stage would need to work for one input voltage only (DC_IN around 7V) while the offset voltage requirement would drop dramatically (stability of 1uV or better). For such a circuit, two feedback loops could be used, one for speed, and one for DC accuracy. However, that doesn't seem to make things simpler with respect to recovery from shorts or output overload

[macaba]

Pulled this from my design archives, maybe have a play around in ltspice?
(developing intuition about circuits is what ltspice is best at!)
Try different compensation/op-amps though the values I have used are a good starting point.

[stephanm]

Macaba, this circuit has exactly the issue I wanted to avoid. When you short circuit the output, the ADA4523 integrator goes all the way to V+ or V- and saturates. After removing the short, you get a huge voltage spike on the output (as low or high as the OP07 can go). It takes whatever time you're setting with your integrator R and C for the circuit to recover, with the given example values, that's several milliseconds. See below for a simulation, where the expected output voltage is 1V. The output gets shorted to ground at t=20ms, the short is removed at t=40ms.

One way to reduce the overshoot amplitude is to feed the OP07 with a weighted sum of the input voltage (V1) and the integrator output. This would maintain DC precision while reducing the overshoot.

[macaba]

Easily solved... back-to-back low-leakage diodes over C1, adjust R3 to give you the current limit you want.
(Component references from my schematic)

[macaba]

See attached, to avoid confusion. Output op-amp and various things changed to reduce the magnitude and duration of overshoot. (Now 100mV and tens of us in width)

[stephanm]

Easily solved... back-to-back low-leakage diodes over C1, adjust R3 to give you the current limit you want.

I halfway agree In this topology, the voltage across the integrator capacitor approximately equals the voltage drop across R3. To avoid that the back-to-back diodes across the integrator capacitor are forward biased, R3 must be kept small, it cannot be used for current limiting. See below for a simulation with Vin=10V and Rload=1k - with R3=100 Ohms (which would already be only a weak current limit!), the diodes across the integrator cap are already forward biased, so that I get Vout=9.7V, pretty far away from the 10V I wanted to see there.

Still, this circuit looks promising. At least it looks an order of magnitude better compared to the last graveyard of discretes and matched transistors around some precision opamps I was working on lately. Interestingly, I was starting with a similar topology, but one where the two feedback loops are arranged differently... The circuit you proposed also seems to play well with capacitive loads (as a quick shot, I found it even better with R4 inserted in my schematic below), and the overshoot behaviour after removing a short looks good.

Maybe I can get away with this circuit using a low current limiter resistor value (such as your 22 Ohms) and just use an op amp with low max short circuit current for limiting output current...

[macaba]

Good point about keeping the value of R3 low, I can only think of extending this massively to include a current feedback loop (bit like SMU control loops!) or using an output device with an acceptable approximate current limit, as you say.

[stephanm]

A question that is now open is: How can I limit the current when shorting the output of the buffer circuit to, say, +30V or -30V?

Would it work to put current limiter circuit (such as a JFET wired as constant current source) to the output opamp's supply rails?

[macaba]

Maybe something like this, inline with the opamp output and another one on the feedback line (without the D2 component shown in the schematic).

[macaba]

I went down a bit of a rabbit hole; I wondered how the R3 resistor could be increased (to act as a current limit) without losing DC-precision (due to leakage through the back-to-back diodes), but still keeping the overshoot under control.

See attached with floating input op-amp to limit the output swing of the integrator... the complexity is creeping up!

[David Hess]

Check out "My Approach to Feedback loop Design" by Phil Perkins which is chapter 22 of Analog Circuit Design - Art, Science, and Personalities edited by Jim Williams.

Perkins discusses exactly what you are trying to do and adds a phase lead network in place of R2 to compensate for a variable capacitive load.

[MasterT]

"- No need for speed: settling times in the order of many 10's of milliseconds are OK"

Your requirements are illogical. Settings time is where circuits behave out of control, so any wrong doing possible - undershot/ overshot/ oscillation/ ringing etc.

 To avoid misbehaviour, settling  time should be as small as possible, that's demand very fast amplifier - GHz GBW and 1000-th V/usec slew rate. Something like LM7171.
 There is no OPA on a market that satisfy all your requirements, and there is a reason - almost not possible to build / or price is not acceptable

[stephanm]

Your requirements are illogical. Settings time is where circuits behave out of control, so any wrong doing possible - undershot/ overshot/ oscillation/ ringing etc.
To avoid misbehaviour, settling  time should be as small as possible, that's demand very fast amplifier - GHz GBW and 1000-th V/usec slew rate. Something like LM7171.

My idea is to have a "friendly" DC voltage source, i.e. one that makes it hard to break or fry things that I connect to it. This is why I am looking for current limits and defined behaviour when the load conditions change, such as low voltage overshoot, in addition to step response behaviour and DC accuracy.

Let's take the following example: Consider a purely capacitive load of 50uF, and turning the output voltage of the DC source from 0V to 10V. Ideally, the DC voltage source would deliver 10.0mA (max current) for a duration of 50ms, after which the 50uF cap is charged to 10.0V. That's a slew rate of only 200V/s - no need for GHz BW or terriffic slew rates. After the 50ms, the output current must be zero to keep the programmed 10.0V on the load capacitor.

If I need to place a GHz op amp into some fancy circuit for getting this behaviour and all the other things on my wish list, I'm fine with it. However, I would not be fine with unfriendly behaviour of the DC source during settling, such as large overshoots/oscillations or currents larger than 10mA or maybe 20mA flowing out of or back into that thing.

[stephanm]

Check out "My Approach to Feedback loop Design" by Phil Perkins which is chapter 22 of Analog Circuit Design - Art, Science, and Personalities edited by Jim Williams.

Hm, this text excerpt rings a bell - I need to look into my bookshelf, I think I have this laying around somewhere here. Thanks for the pointer!

[MasterT]

So, what you describe is regulated  bi-polar voltage source with current limiting.
App. note from BB (TI) : ADD CURRENT LIMIT TO THE BUF634   By David Jones and Mark Stitt.


There are also an IC with output current adjustment like LMH6732

[David Hess]

To avoid misbehaviour, settling  time should be as small as possible, that's demand very fast amplifier - GHz GBW and 1000-th V/usec slew rate. Something like LM7171.

Settling time is dominated by the loop response produced by C1 which is required for stability.  Replacing U1 with a faster amplifier will not help.  C1 also causes integrator windup when the output does not follow the output of U1, so there are two components making up the settling time.

This is the same problem constant voltage constant current power supplies face and it has the same solutions.  One common solution is to use an operational transconductance amplifier in place of the operational amplifier because the current output can be used to avoid windup.

[MasterT]

"Settling time is dominated by the loop response produced by C1 which is required for stability.  Replacing U1 with a faster amplifier will not help.  C1 also causes integrator windup when the output does not follow the output of U1, so there are two components making up the settling time.
"

I see it from the other side.  Load transient step response is what important in this application, especially in absence a capacitor at the output (like slow voltage regulators have)  and step response (cranking current suddenly)     completely defined by OPA output stage driver speed .  Having slow OP07 demands C1 in first place, just to buy time for output stage to react, other-ways inputs stage gonna to be hardly over driven and time that needs to recover would be even more than initial limits from outputs stage

[David Hess]

I see it from the other side.  Load transient step response is what important in this application, especially in absence a capacitor at the output (like slow voltage regulators have)  and step response (cranking current suddenly)     completely defined by OPA output stage driver speed .  Having slow OP07 demands C1 in first place, just to buy time for output stage to react, other-ways inputs stage gonna to be hardly over driven and time that needs to recover would be even more than initial limits from outputs stage

Both U2 and the load capacitance add delay within the feedback loop requiring C1 if U1 is fast enough.

An OP-07 is really the wrong type of part for U2; a better choice would be an LT1010 buffer, or a diamond buffer, or maybe an inexpensive current feedback operational amplifier configured as a follower.  I would likely use a discrete buffer like the first example shown below.

D1 and D2 provide current limiting of the output by limiting the voltage across R9 and R10.  LEDs could be used if the supply voltage is high enough.  Current feedback through the R1 and R2 network controls the voltage gain of the output stage and provides a low output impedance despite the high impedance of the transistor collectors.  Of course I would adjust all of the values for lower gain and lower output current operation.

[macaba]

OP07 is not the best part and that is intentional.

Stephan asked for practical circuit ideas, OP07 = cheap, single part, built-in current limit, simulates well. I don't see much hollistic practical advantage with the more complex circuits (especially replacing 1 part with tens of parts!) though I understand the allure of theory. I am sympathetic to the idea that maybe a faster buffer could be better, perhaps there is a jellybean part that could go here instead.

[MasterT]

OP07 is not the best part and that is intentional.

Stephan asked for practical circuit ideas, OP07 = cheap, single part, built-in current limit, simulates well. I don't see much hollistic practical advantage with the more complex circuits (especially replacing 1 part with tens of parts!) though I understand the allure of theory. I am sympathetic to the idea that maybe a faster buffer could be better, perhaps there is a jellybean part that could go here instead.

 Right, OP07 has 60 uV typical offset, so I don't see a reason to complicate circuits by 2-nd  AZ op-amp like ada452x.
 If priority is precision, then  any audio jelly been could be in use with ADA452X, NE5532 / NE5534 for example.

Returning back to original "1-opa" buffer posted in first message, the way circuits may be improved. The issue I see is comming from output protection requirements. Easiest solution - zenners & resistors to "cut & dissipate" - power (in case +-30V connected) should be carefully evaluated. Since current limiting resistors value can't be too high - 10mA already ask for < 500 Ohm is 5V drop-offf is allowed.  And 15-18V over 500 Ohm P = 0.648 W.

 Certainly protection circuits creates stability & precision problem, so capacitor & negative feedback from other end - bad things for the speed brought back, see attachments.

 Thinking about recovery time after OPA driven out of linear range to saturation, capacitor has to be dischraged quickly or prevented from overcharging, and something like "out of linear range" detector may be necessary.
Circuits that would monitor ouput above /below 12V and switch "internal" negative feedback with "overload" indicator to user

[David Hess]

Right, OP07 has 60 uV typical offset, so I don't see a reason to complicate circuits by 2-nd  AZ op-amp like ada452x.
If priority is precision, then  any audio jelly been could be in use with ADA452X, NE5532 / NE5534 for example.

The precision of U2 is irrelevant because it is within the feedback loop which removes U2's offset.  It's noise is also removed within the bandwidth of the feedback loop.

Thinking about recovery time after OPA driven out of linear range to saturation, capacitor has to be dischraged quickly or prevented from overcharging, and something like "out of linear range" detector may be necessary.

That is commonly known as anti-windup.  Clamping can be used if the operational amplifier supports it, like the LM301A or an operational transconductance amplifier.  Integrated regulators often use the later for exactly this reason.

[MasterT]

Right, OP07 has 60 uV typical offset, so I don't see a reason to complicate circuits by 2-nd  AZ op-amp like ada452x.
If priority is precision, then  any audio jelly been could be in use with ADA452X, NE5532 / NE5534 for example.

The precision of U2 is irrelevant because it is within the feedback loop which removes U2's offset.  It's noise is also removed within the bandwidth of the feedback loop.

 You didn't get it. What I say, is OP07 is precise enought to work alone, single, got it?

 Noise is also a problem, circuits with two opa's in series has a "bump" on a frequency/magnitude chart. Better way to correct offset is to put precise op-amp not in series but "in parallel".
Doing so frequency responce is not touched and what is more important, not limemited by low speed az amp.

[David Hess]

Stephan asked for practical circuit ideas, OP07 = cheap, single part, built-in current limit, simulates well. I don't see much hollistic practical advantage with the more complex circuits (especially replacing 1 part with tens of parts!) though I understand the allure of theory.

I suspect the more complex circuit will be simpler than what will be required to make an unsuitable circuit work properly.

I am sympathetic to the idea that maybe a faster buffer could be better, perhaps there is a jellybean part that could go here instead.

I gave a couple of examples of suitable parts to replace U2.  They will be an improvement but will not solve the inherent problems.

[stephanm]

Thanks for all the input so far. The one-op amp circuit I showed in my first post was meant to illustrate one of the issues that I found when trying to design a circuit with low over-/undershoot on load changes and input voltage changes, it was not meant to give an upper limit in terms of circuit complexity that I am willing to take

I played around a bit with the circuit discussed in "My Approach to Feedback loop Design" (suggested by David Hess), but I found it hard to find the right tuning knobs to get the behaviour I wanted, especially when adding series current limiting to the output and letting the load come out of a short circuit, or, to put it in a more general way: When the load conditions change. This seems to be something that is not discussed often in the literature I have found so far (thus the question here in the forum.) Regarding the suggestion to look into OTAs - I'm not familiar with them and it might take me a while to do some reading and circuit simulation based experimentation.

In the meanwhile, I restarted from scratch and came up with a circuit sketch that, so far and only in simulation, is closest to my initial specs. While doing so, I also understood that a major source of issues is my unwillingness to add an output capacitor to the DC buffer's output - keeping the voltage overshoot after a short on the output under control with a 10nF or 100nF capacitor at the output is much easier that without one. For a practical realization of the circuit I am thinking of adding a switch to connect or disconnect a built-in output capacitor, allowing the user to choose between:

- low voltage overshoot on load changes (output cap connected; the price is that the output cap can discharge into the connected circuit and produce a potentially intense current spike), or
- higher voltage overshoot e.g. after output overload conditions, but not so much charge being dropped on the load when the load suddenly becomes low impedance

To avoid ever growing complexity of a final circuit, I am also willing to weaken some of my initial specs, at least up to a certain point. It's, as usual, a tradeoff...

While still missing some things, here's a brief description of the circuit I have in mind at the moment. The DC input is actually at the bottom right of the schematics. The input voltage is fed into an op amp voltage substractor (U4) which is used to compensate for the voltage drop across the output current limiter network (Q1, Q2, R2, D2 / R6, Q6, R13, D3). U4's output voltage goes to the unity gain buffer U1 through R1 (1k). Note that U1 has only local feedback, the LT1220 I have placed there could probably be replaced by some other fast unity gain voltage buffer (discrete or integrated).

The voltage drop compensation provided by U4 is actually less than what is needed for DC precision, as it doesn't account for the voltage drop due to U1's finite output impedance and U1's offset and bias current related errors. To compensate for this, the integrator U2 adds DC precision - it's output voltage will, through R12 (220k), provide the necessary correction to U1's input voltaqe to maintain DC precision. The LTC2057 is probably overkill here unless µV precision is wanted or needed. On the other hand, looking at the price tags of the op amps I am currently simulating with, the LTC2057 is not my biggest concern at the moment!

Due to the high ratio of R1 to R12, U2 can only provide a small voltage correction. This means two things: First, the voltage errors by U1 and U4, included their sourroundings, must be small enough so that U2 can maintain DC correction without saturating. Second, if the output voltage is far off the REF (input) voltage, U2 will saturate at it's supply voltages, but due to the high R12:R1 ratio, this won't have too much effect on U1's input voltage.

The unfinished part of the circuit is the differentiator part around U3 and the clamping network around D1 and D4. On the left side of D1 and D4, two voltages must be provided for clamping U1's input voltage: REF+X and REF-X. Here, X is given by the maximum voltage drop across the series current limiter circuit (roughly 2V.) Now, what's the differentiator U3 doing? If the output voltage goes up, U3's output will become negative, and the clamp voltage will be reduced, slowing down the voltage change on the output and thus helping to keep voltage overshoot low.

While I wouldn't be surprised if the circuit characteristics will get worse once the clamping network is translated into real components, simulations so far show that I am at least somewhat close to the initial specs. While this means that I'd be failing to meet the requirements I initially stated, chances are that I have something reasonably close to that before the end of the year

Looking at the simulation results I have seen so far, output current with shorts to voltages between in the +/-30V range stays below 30mA, and capacitive loads up to 100µF seem to be handled stable, although one has to accept some settling times. Response to small and large steps in the input voltage look ok as well, and is even compliant with my original specs at least if the load includes a capacitive part with some many nF or more. Response to load changes (coming out of overload conditions, for example) is ok-ish, again as long as some many nF of capacitive loading are provided. Without a load capacitance, the most critical conditions are small input voltages such as REF=100mV, and instant load changes from short to open. In such situations, the output can overshoot by more than 1.5V for 50ns followed by some phase of 1 to 2µs where the output voltage exceeds REF +/- 200mV.

As a next step, I'll fill out the missing parts of the circuit and see what I get.

[David Hess]

I played around a bit with the circuit discussed in "My Approach to Feedback loop Design" (suggested by David Hess), but I found it hard to find the right tuning knobs to get the behaviour I wanted, especially when adding series current limiting to the output and letting the load come out of a short circuit, or, to put it in a more general way: When the load conditions change. This seems to be something that is not discussed often in the literature I have found so far (thus the question here in the forum.)

The author mentions using SPICE to optimize the results, and I would have used some bode plots by hand to start off with.  The 3dB/octave network to increase phase margin is about small signal stability at the expense of bandwidth, so the output capacitance will never make the circuit oscillate, but something still has to be done about overshoot caused by windup.  This loss in bandwidth is less than if dominant mode compensation is used.

Regarding the suggestion to look into OTAs - I'm not familiar with them and it might take me a while to do some reading and circuit simulation based experimentation.

Unfortunately there are no general purpose OTAs for this sort of application.  Switching regulator controllers often use them however and expose the needed signals.  The LM723 regulator has one so that might be an option.  The LM301A operational amplifier can be used as one by substituting its compensation pin for its output, but I have not actually tried this.

The power supply regulator circuit shown below shows two things for consideration:

1. The output compensation is a 0.22 microfarad - 10 ohm series network, so the current limiting response is faster than it would be otherwise.
2. The LM101A (same thing as an LM301A) used as the current error amplifier is clamped through its compensation pin (pin 8 as shown) preventing windup in voltage mode, so that the current limiting operates more quickly when the load shorts.  This is similar to the advantage of using operational transconductance amplifiers.  Clamping in this case means that the LM101A output cannot move more positive than one diode voltage drop (D2) over the output of the LM308 which is used as the voltage error amplifier.

Linear Technology makes a power operational amplifier intended for your application which might be worth studying.  It includes a voltage controlled current limit:

https://www.analog.com/en/products/lt1970.html