Usb Differential Pair Routing

[benwis]

Hi everyone,
I'm laying out a USB 2.0 fullspeed interface, and had a question about how to setup the impedance matched differential pairs.
I know that they need to be 90 ohm controlled impedance, and they need to be length matched.

But how do you handle series resistors and additional resistances on the differential pairs?
The data lines essentially go from connector to a TPS2540 to handle USB2 CDP handshaking, then through 22 ohm termination resistors to a max3421e USB to SPI transceiver. Which part or parts of that chain should be 90 ohms? 90 ohms up to the series resistors? 90 ohms including the resistors, or something else.

Thanks for any advice,
Ben

[benwis]

Hi,
Thought I'd post a schematic of the USB part of the board. If no one answers, I think I'm just going to do the 50 ohm impedance traces to the series resistors, and place them as close as possible to the MAX USB transceiver. I'll let you guys know how or if it works.

[kubeek]

Yes the resistors need to be close to the transciever and the tiny length of trace between the resistor and pin doesnt really matter.

[tszaboo]

I have routed USB with "just close together" design rule for 20-30 cm on a PCB with no issues whatsoever. That 12 MBit speed allows you to do a lot of stuff.

[T3sl4co1l]

If your USB host/interface/PHY device does not have internal series resistors, and you are only using up to Full Speed (USB 1.1 / 2.0-compatible), then:

Get a one of those USB filter and protection devices, such as:
http://www.digikey.com/short/34v0rz
(They vary by ESD rating, size, capacitance, resistance, and the having-or-not of pull-ups/downs.)

Place it near the PHY (within some ~cm?).

The filter should roll off around 30MHz, because Full Speed is only 12Mb and therefore needs >= 6MHz bandwidth.  Filtering saves you some trouble with RFI and transients, and the kind with internal clamp diodes or zeners further protect the PHY device against transients.

The traces, between filter and connector, should be nominal impedance (40-50 ohms each, with a little differential coupling), but, since the signal's been filtered, you aren't very concerned with what happens to the signal in the 100s of MHz range -- which means, up to about a meter in trace or cable length, you really don't care much where the signal goes, or over what impedance -- put it on loose wires for all anyone cares!  (As long as it's still shielded, so RFI doesn't leak out, or strong interference leaks in.)

The same method applies to any signal of up to modest bandwidth -- digital GPIOs, SPI, RS-422/485, Ethernet (10Mb, and 100Mb with proportionally shorter "don't care" trace lengths) and so on.  As long as you clamp transients, filter noise (incoming and outgoing), using only the bandwidth you need for the communication channel to operate -- you will have the least possible amount of problems!

Tim

[kubeek]

Why would 12Mbit need only 6MHz of bandwidth?

[T3sl4co1l]

Worst case, alternating bits: if it toggles at 12MHz, the frequency is 6MHz.

You might want more bandwidth (or at least a special filter) to reduce inter-symbol interference, i.e., get sharper square waves with less "drool".  So more bandwidth is okay, but more than 20MHz or so isn't really needed.  Which doesn't help with conducted emissions or susceptibility, but does help with radiated, so that's definitely a plus.  (High speed requires 100s of MHz of bandwidth, so although it can still benefit from some filtering -- useful if your device has a Wifi radio in it, say -- it doesn't save you much, otherwise.)

Tim

[iromero]

I'd think they chose 30Mhz as the 3dB point because it's the fifth harmonic of the fastest signal, which would make it look still pretty square.

[T3sl4co1l]

Yup, and the RC filtering is pretty gradual, so it doesn't kill squareness all that fast either (nor kill RFI significantly until >100MHz, but oh well).

If you want a tighter cutoff, then you need an ever-higher order filter, as the cutoff frequency approaches 6MHz.  To do it at 6MHz, you need a brick-wall filter, which is unrealizable.

This, by the way, might sound suspiciously like ADC antialiasing filtering, which is no accident: it's the same thing, whether your ADC is one bit (a comparator or digital input pin) or many!

In this case, we don't want to filter out aliasing signals (i.e., harmonics), because we specifically desire those in the signal: as long as they remain in phase, they improve SNR.

However, a poor filter will phase shift them all over, and degrade SNR, which is why it's desirable to have the cutoff frequency higher by some margin.

(Other applications include VGA to LCD digitizer circuits, or Gb Ethernet, where the signal is multi-level, and filtering degrades the bit-to-bit SNR.  Digital control loops need low phase shift in the loop, and don't much care about high frequency or aliased noise, so tend to use the same filtering strategy.)

Tim