I Have Done IT! (Increased the speed of a serial task)

[mrflibble]

I think you should look into FPGAs, massively parallel algorithms can be quite powerful, but also inflexible.

I have looked into FPGA's. But, I haven't any education in Verilog in the slightest. I have taken C classes... So I modeled it in C. I haven't been able to self teach myself Verilog.... All the tutorials online kinda suck for newbies like me. They all rely on you taking a class at uni and they go alongside with that. And also consider that here in NM, there isn't any kind of a VLSI school.

FPGA recommendation seconded. They are a very good fit for this sort of problem. As for learning verilog ... just a book or two + online tutorials + lots of try and fail and try again can do the trick as well. No need for a formal HDL program at uni. I used "A verilog HDL primer" from Bhasker to learn the basics.

Not that I am now the world's greatest HDL coder, but at least it's better quality than opensores.org  I know, I know, setting the bar low.

*grin* Just checked, and opensores.org actually exists. XD

As for the matter of getting a review, peer flavored or otherwise ... working on readability of code + having a good design document really helps there.

And yes, please use caps even if your switching rate is low. Fast logic will still cause transients that can cause all sorts of funky stuff where you least expect it. And generally speaking ... TTL probably even more so than CMOS, due to more charge being pumped around.

[adam1213]

That's weird.... I should have caught such a blatant error. Stupid GCC didn't even give me a seg fault..

I wish all invalid memory accesses would be easy to detect rather than occurring silently.

Segmentation faults occur when a program attempts to access a region of memory in its world (address space) that it's permissions don't allow. Accessing memory outside a given array won't always cause a seg fault as the region may be permitted.

If you want gcc to be clever and warn you about most memory accesses issues you can use mudflap. To use it compile using "gcc  ....normal flags... -fmudflap -lmudflap"
 * getting mudflap to work may require installing packages (e.g. libmudflap0)
 * mudflap will slow the execution of a program down as it performs run time checks

[mrflibble]

I vaguely recall there being some issues with libmudflap and multi-threading. Other than that, using something like mudflap is a good idea if your code is  a bit creative in the memory management department...

Oh and pedantic point .... gcc won't segfault due to your code content. It's your runtime binary that does the segfaulting. If your gcc segfaults you have bigger issues. ;-)

[Mechatrommer]

the worst? bugs turn into features!

[mrflibble]

You mean like termites and "topological features" in wood?

[adept]

Mechatrommer, I have a block diagram attached to one of my later replies. It shows visually the information that I used in my head to come up with the design.

Code commenting is under way. I started the program over again and am having problems with getting the recursion to work. The new program isn't working as I want it to yet. I'll post it when I get that to work correctly. My brother should be able to help... he is a CS major after all!

I gotta say that mudflap is a pretty funny way of thinking about what is happening here! It is catching all the "mud" that is your code from getting all over everything! Anyway, I tried it and it indeed returned an error with my code. Go figure. That is definitely something I'll be sure to check before I post any more source with the working recursion algorithm.

Anyway, not much time to work on anything important tonight. It's the middle of the high school work week and I have other things to worry about before Saturday! (AP US History... curse the irrelevancy of high school courses to real life!)

[adept]

I've slopped together a very rough rough draft of the paper I need to submit by Friday. It took me all day, but it's there. There are some semi-major flaws in it that I found already but don't feel like fixing tonight. The equation on the last page that gives the number of cores is missing a summation 1 to k on it and the abstract has a header and it shouldn't.... It's definitely got some work to do. But it is the first copy I have that is under the word limit and contains all the required information. Hope you guys tear it to pieces!

Cheers

[mrflibble]

Seeing how it is past the previously mentioned Friday ... how did that go?

During a quick read I noticed a few things, but chances are you already have a better version. Anyways, you may want to read up on speculative execution and speculative branching, since some of the claims of "X has never been done before" I found to be a bit ... inaccurate.

Oh yeah, as for simulation. You may want to look into an evalutation version of modelsim. Or maybe ISE or Quartus from Ye Olde FPGA Vendor. You can still do schematic capture there if you want to, and for bonus points you can start dabling a bit in verilog or vhdl.

[adept]

The recursion algorithm didn't ever get working. So I continued with all the other simulations I had and finished off the paper whose deadline was looming. I am literally being swarmed with different busy things to do.
The speculative branching is not exactly like this at all... It does indeed use the same concept as speculative processing, but it does all of this at the hardware level. This is something a step above and beyond what old methods have used. So the answer is yes, some aspects are unoriginal, but there is at least something about it that hasn't been done in the past.
Modelsim is new to me. I am a student, so I think I can get a copy for freebies. But today is a busy day. Tomorrow will yield more time to look into that further. Gotta go to mass in a bit....

TTYL

edit:

This is a graph that shows the return of adding more stages. It all experiences a severe diminishing return. The amount of power for a very tiny increase in speed is enormous. Just thought that you guys might be interested in seeing a diagram showing some of the results I have. Notice that it is not even linear on this logarithmic scale. It has a curve to it because it is a limit of a summation. An integral if you will. The stages are cumulative.... Hope you guys like it!

[AndyC_772]

You can get ModelSim for free by downloading the Web edition of Altera's Quartus II development software. It has some limitations on code size and simulation speed, but it's still a very useful and capable tool.