SERDES problems at higher frequencies

[AndrewHodgson]

Hi,

I'm trying to help a friend out with a SERDES issue, but my knowledge of the problem is not great, so you'll have to forgive me if some details aren't very clear.

Basically, they have a SERDES link between two FPGAs that fails when the comms frequency is increased to 6.25 GHz, it works Ok at 3 GHz.

The FPGAs are supplied by two separate low jitter clocks (PLLs) that in turn are fed by a low frequency oscillator. When the FGPAs are fed by the same clock (PLL), the link works at 6.25GHz. 

My question is does this sound like it's related to jitter? The low frequency oscillators have a buffer prior to the PLL with a cycle-to-cycle jitter of 200 pS max. Is this jitter likely to be passed on through the PLL and cause issues with the comms link at higher frequency? My understanding is the receiver can tolerate about 0.5UI jitter so this figure would be in the right range to cause an issue?
Any other thoughts would be much appreciated.

Thanks in advance