Project Advice For RA8875 SPI & Teensy 4.1

[ryanmills]

Working on a board that will drive at least 5 displays via 4-wire SPI from a Teensy 4.1. The displays have the RA8875 chipset. I'm more of a software guy than a hardware guy and could use application advice. I attached my starting schematic below, its missing pull resistors, caps, ect but show the basics. The goal of the project is to push different bitmaps to each of the screens based on button pushes. I have been reading up on Paul Stoffregen's dive into the SPI implementation on the RA8875 and its bugs. Since I plan to add an SD card via SPI in the future it sounds like some extra work is required.

For my question, I have not worked with buffers before, the 74HC125 is recommended in everything I read but since it only has 4 elements it's not ideal for my application. I don't understand the root issue well enough to substitute it. I also could not find an example of how you might chain them so I could use 2, if that is even possible. I did find an example using one per screen and that's what I'm using at the moment. Is it possible to chain up two 74HC125's instead using five? Or is there another common buffer better suited to 6 or more elements? Second, to save ports I added a multiplexer for the CS. Will that cause any timing issues with the SCLK timing?


Display: https://www.buydisplay.com/5-inch-tft-lcd-module-800x480-display-controller-i2c-serial-spi

[moffy]

Your link generates a 404 error. Not sure what the work around is for then, I'll have a look for Paul Stoffregen then.

[moffy]

Having looked a bit more into it, the reason for the 74HC125 is to provide isolation for the 4 SPI signals from the RA8875 when the particular RA8875 display is not selected. That is done by applying a 1 to the 4, /OE pins of the 74HC125, which tristates(places in high impedance) its outputs. There is probably a bit of redundancy in the implementation, as the SPI inputs (CS, SCK, MOSI) don't need the tristating because the RA8875 shouldn't hold them high, but there might be other reasons for isolating them.

[ryanmills]

I got some feedback that cleared up a few of my questions and I have updated my progress. If anyone has worked with SPI, the RA8875 chipset and bug. Does my tri-state buffer look correct?

[ryanmills]

Having looked a bit more into it, the reason for the 74HC125 is to provide isolation for the 4 SPI signals from the RA8875 when the particular RA8875 display is not selected. That is done by applying a 1 to the 4, /OE pins of the 74HC125, which tristates(places in high impedance) its outputs. There is probably a bit of redundancy in the implementation, as the SPI inputs (CS, SCK, MOSI) don't need the tristating because the RA8875 shouldn't hold them high, but there might be other reasons for isolating them.

Sorry Moffy, I did not refresh the page before I posed my updated schematic yesterday. Thank you for taking the time to review it, I also fixed my link. I might be confusing myself but I think I have it correct now in the schematic above. One thing I'm not grasping, given these are displays and in the end I'm just writing to the registers not reading from them do I even need the SDO from the displays?

[SiliconWizard]

As far as I can tell, the only line needing tri-state buffering would be MISO, because if I read it right, the RA8875 itself does not tristate it. And, that would matter only if you plan on sharing the same SPI bus with other peripherals - otherwise it's not even needed.

[moffy]

As you suspected and SiliconWizard stated, not needed for normal use, but might be useful for debugging purposes if you need to check data or registers.