### Author Topic: Circuit design problem  (Read 406 times)

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#### khatus

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##### Circuit design problem
« on: August 11, 2018, 08:01:07 am »
Currently i am designing a PCB board for my new project. But the problem is, the chip or ic i'm using has the following connection for Supply in it's data sheet (it's common ) the entire bottom layer is ground plane.

Three, same type of Ic will be used for my project.I connected them with 12V supply in the following manner as shown below

But later i thought another kind can also be used like this

But Now I am little confused which connection should i use?? What will be the difference if i use connection-2 instead of connection-1.

In the second connection i used a 0.3 uF capacitor with the supply. since the capacitor(0.1uF each of them) connected across VCC and ground of each individual IC's are in parallel.
3*0.1uF = 0.3uF.

Can Someone explain, which circuit will function properly?and why?

NB: the ic's are IR2110 Mosfet driver.
« Last Edit: August 11, 2018, 08:02:46 am by khatus »

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##### Re: Circuit design problem
« Reply #1 on: August 11, 2018, 08:19:38 am »
That's not how decoupling capacitors work. They only actually useful if they are close to the power pin. You need a separate capacitor for each IC. On more complicated ICs with multiple power pins, you need  a separate capacitor per pin.

The circuits are not equivalent, and the second one is wrong.
Alex

#### ArthurDent

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##### Re: Circuit design problem
« Reply #2 on: August 11, 2018, 08:27:21 am »
This EEVBlog video has some good information. Depending on a lot of factors (frequency, switching speed, etc.) you might be able to get one cap to work but it's generally considered bad practice.

#### khatus

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##### Re: Circuit design problem
« Reply #3 on: August 11, 2018, 08:32:26 am »

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##### Re: Circuit design problem
« Reply #4 on: August 11, 2018, 08:37:21 am »
Yes, sure. Whether you need it or not depends on your supply.

And you don't need to use electrolytic capacitors for the bypassing, ceramics will work fine.
Alex

#### ArthurDent

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##### Re: Circuit design problem
« Reply #5 on: August 11, 2018, 10:17:43 am »
The video I linked to in post #2 answers the question of adding an electrolytic as well.

#### T3sl4co1l

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##### Re: Circuit design problem
« Reply #6 on: August 12, 2018, 05:13:13 am »
That's not how decoupling capacitors work. They only actually useful if they are close to the power pin. You need a separate capacitor for each IC. On more complicated ICs with multiple power pins, you need  a separate capacitor per pin.

The circuits are not equivalent, and the second one is wrong.

Only "wrong" in the dogmatic sense that it violates someone's arbitrary condition.

It's only "wrong" in the true practical sense, if it causes the ICs to malfunction, however that might be.  Examples might include: excessive supply or output ripple/noise, digital jitter, DC offsets in op-amps, etc.

In practice, the bypass caps can be many decimeters away from the device in question.  Or maybe they have to be right up against the device, and multiple are required.  Or furthermore, multiple are required, and they must be arranged around a supply plane with lossy capacitors as well,

How to avoid the dogma and approach it analytically?

First, determine how much ripple the device should experience.  This will probably be less than 10% of total supply voltage, but beyond that, it depends.  A sensitive analog circuit will need its supply quiet enough, so that, supply noise * PSRR does not affect the output noise floor.  Use PSRR (which is a function of frequency!) in your calculations, where possible.  Digital gates should be considered as 50% PSRR, i.e., CMOS input threshold is at about half supply.  An analog or digital circuit with very good PSRR (like emitter followers, and ECL) might be perfectly fine with relatively noisy supplies, even for relatively critical (sensitive or low-jitter) applications.  You won't know until you calculate the requirement!

Second, determine how much transient current the device will draw.  This also varies wildly with type.  An op-amp will be fairly quiet, except for load current being passed directly to the supplies (for obvious reasons).  Therefore, an op-amp with a heavy load will generate more transient supply current than a lightly loaded one.  By transient, I mean that only changes in current matter: the DC (quiescent / operating) current need not be a factor.  An opamp might draw, say, 3mA operating current, but source/sink 30mA into the load; an ECL gate might draw 10mA, but as long as the outputs are loaded equally, that current draw hardly changes at all; a CMOS gate might draw 100uA average, but gulp pulses of 2 or 20 or even 100mA ("shoot-through current") when the outputs switch state!

Third, put these two factors together to find the maximum supply impedance, ΔV/ΔI.  Assume that this impedance must be met at all frequencies of interest to the device.  An LM741 might only be critical up to 10MHz (and basically ignorant of anything above there).  A CMOS gate might be critical at more than 200MHz.

Incidentally, it is simply physically impossible for a PCB to deliver stable power to heavy loads, at frequencies much above 100MHz -- as a result, big, low voltage devices, like MCUs, FPGAs and SoCs, have on-board bypass caps inside their package, even on die, to supply their GHz-range current demands!  At frequencies this high, the length of the device's own pins prevents any degree of PCB-level bypassing from helping up there.  Consequently, don't beat yourself up if you can't get a bypass cap on every single stupid pin!

Fourth and finally, synthesize a PDN (power distribution network) that meets the impedance requirement.

What is a PDN?  It's a chain of series inductors (trace inductance) and parallel capacitors (bypasses, planes) connecting power to devices.  In other words, an ordinary dumb LC filter.  What do you do with a filter?  You terminate it, at its characteristic impedance, and it behaves.

To make a good filter, place bypass capacitors at more-or-less regular intervals (distances) from each other.  Prefer a linear (point-to-point-to-point, single chain) topology with termination at one or both ends, or use a branched topology (some points connect to multiple other points) with termination at the ends of the stubs.

This isn't hard.  Computers can do this analysis for you.  (Given some setup, of course.  Computers aren't THAT smart yet.)  Why do people prefer dogma?  Because people are lazy, and better at pattern recognition ("these caps don't look right"!) than analysis.

With some practice, you can run through this list in ten minutes.  It's not a big burden.  It can be greatly accelerated with assumptions and shortcuts -- keeping in mind the limitations of those assumptions, and being careful not to fall back into a dogmatic approach yourself.

Tim
Seven Transistor Labs, LLC
Electronic Design, from Concept to Layout.
Need engineering assistance? Drop me a message!

#### rstofer

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##### Re: Circuit design problem
« Reply #7 on: August 12, 2018, 07:28:42 am »
Since the back side is ground, I usually put the decoupling capacitors back there.  I can get very close to the Vcc pin and ground is all around.  Using SMD, of course.

Smf