Hi fellow electronics enthusiasts!
I am a student working in an optics lab where much of my time is spent developing FPGA systems for data acquisition, experiment control and data processing. Now, I have been tasked with developing an interface board that is able to drive 50Ω loads with either pulses or a waveform, (sine/triangle etc) and all I can say is; analog electronics is difficult!
This is my first time designing, in an organized manner, something that is a) high-speed and b) using multiple IC's, so I would really appreciate any advice both on component selection and circuit topology before I start laying out the board.
I have simulated the circuit (apart from the LDO regulators and the analog switch, for which I was unable to find working SPICE models), and it indeed behaves as I would like, but I have a feeling that there are many traps that I surely must have fallen into.
The problem (In order for me not to fall into the XY-trap):
I would like to send narrow (~10 ns) pulses to an electro-optical modulator (EOM,
https://www.thorlabs.com/newgrouppage9.cfm?objectgroup_id=3918) which is 50Ω terminated. In addition, I would also like to set the amplitude of said pulses, or drive a non-pulsed signal (does not need to be very fast) into the modulator.
Using a benchtop function generator is easy enough, but I would like to control the signal send to the EOM using my FPGA (Zynq-7020). For my use case, I would like to drive voltages between 0 to ~6V, and naturally the FPGA's GPIO pins cannot source the current necessary for that.
Let me illustrate two use cases I have in mind:
UC1: I want to output a waveform to the modulator using the FPGA in the range 0-6.6V
UC2: I want to output narrow pulses with a digitally-settable amplitude to the modulator
The general idea:- Use a DAC to set the amplitude (0-3.3V output) or drive waveform from the FPGA
- (Optionally, "chop" the DAC signal into pulses if I want to feed a pulsed signal)
- Amplify and buffer the 0-3.3V signal to the full range (0-6.6V)
Schematic:
(Schematics are attached below the post)
Below are the design choices that I made when choosing the components and designing the blocks in the schematic, as well as some comments on the process.
"DAC":
Here I have opted to use a simpler DAC, which I already am familiar with from the Digilent Pmod DA2, and I figured that, since the digital switch will do the high-speed switching, the DAC itself doesn't need to be fast. The DAC is powered using the 3V3 rail from the FPGA, and the FPGA ground is connected to the GND net on the board.
"Pulse generator ('Chopper')":
Fastest SPDT switch I could find. When the PULSE pin is high, it will output the voltage at pin B1, and be grounded (output 0V) when the pin PULSE is low. My understanding is that it works almost like a mechanical switch, where the signal is directly fed through when the switch is closed. If this assumption is true, then I would be able to drive a waveform from the DAC straight through the chopper by leaving the PULSE pin high, but also generate pulses by outputting a voltage using the DAC and rapidly toggling the PULSE pin. The motivation for using an analog switch in lieu of something transistor based is that I was unable to design a transistor circuit to switch the signal adequately. :-)
"Gain + 50 ohm driver":
Fast op-amp that is capable of supplying high currents, but a drawback is that it is not rail-to-rail, hence the peculiar VCC/VEE using two LDO regulators. The voltage swing is around 1.2-1.3 volts from the supply rails. The absolute maximum supply voltage is 12.6 V. The feedback resistor is a trimpot in order to be able to adjust the gain, but at 50% setting it should give a gain of G=2. I've placed a 2pF capacitor to ground as suggested in the datasheet. It seems really difficult to find an amplifier that has both i) high bandwidth, ii) high input voltage range, iii) rail-to-rail, iv) can drive 50Ω. Capacitor choices on the power rails are heavily
"+8V Supply" & "+2V Supply:
Linear regulators because I want to limit noise that could be amplified by the op-amp. I am very unsure about generating the power rails for the op-amp this way. It just does seem like the right way to do this, but I need a negative supply voltage to the op-amp. 10uF capacitors to ground, but I am really unsure about the values here.
Power supply:
I intend to power the voltage regulators with a 12 volt wall plug.
Connectors:
12 pin straight header that plugs into a Pmod header on the board used to control the DAC and trigger the pulse. Barrel jack for the power supply. SMA connector to connect to the equipment using a standard 50 ohm coaxial cable.
Component datasheets:
Operation amplifier (AD8009):
https://www.analog.com/media/en/technical-documentation/data-sheets/ad8009.pdfAnalog switch (PI5A3157):
https://www.diodes.com/assets/Datasheets/PI5A3157.pdf8V regulator (BD80GA5WEFJ):
https://fscdn.rohm.com/en/products/databook/datasheet/ic/power/linear_regulator/bdxxga5wefj-e.pdf2V regulator (BU20TD3WG):
https://fscdn.rohm.com/en/products/databook/datasheet/ic/power/linear_regulator/buxxtd3wg-e.pdfQuestions:- Is this a sensible approach to solving the general problem? I have a funny feeling that there might be better ways.
- Are the decoupling capacitors properly sized? C3 is an electrolytic capacitor in the datasheet, does this matter?
- Is there a better way of solving the power supply for the op-amp?
Conclusion:
I have waded through a bunch of different components like line drivers, MOSFET circuits, BJT circuits and also tried altering the order of the blocks, and finally landed in this design here. I don't really know how to proceed anymore, and I would appreciate any pointers in the right direction.
Sincerely,
A graduate student who is lost in the analog forest