CMOS IC - ESD protection

[EECrAZY]

I was taking apart an ancient IC (1.2 um CMOS n-well process) and came across this ESD protection structure. Any ideas what it can be?
With the FOX etched away:
Green areas are protruding above field and are likely diffusions
Black areas appear to be recessed, so I assumed they must be n-wells, but they are way narrower than allowed by design rules for this tech level.
These structures are always placed in pairs next to each other, 1 half connects to+5V, another to GND. At another location 1 half connects to pad and another one to +5V

Is that an SCR voltage clamp or something else?

[EECrAZY]

Could it be a snapback type voltage clamp?  So both diffusions are n-type, and black areas are indeed n-wells.

[amyk]

Diodes.

[EECrAZY]

Diodes to Vdd rail are typically placed entirely inside of the n-well tub, with p+ anode in the middle and n+ cathode surrounding anode on 3 sides.
After quite some googling, found this so called "SNAP" structure which looks nearly identical to my IC and the only reference to structure with n-well inside of n+ I could find. It was noted that  both n+ diffusions must be spaced at minimum allowed distance, so "active edges" are as close as possible. So from what I understand, it forms n-p-n structure which "snaps" once certain voltage between closely spaced n+ areas is exceeded.

Any one has any insights on these structures and how do they operate and how are they designed? Thanks!

[TimFox]

Probably not directly relevant to your device:
Back in the 1970s, when RCA introduced the 4000 series “COS-MOS” devices, I attended a talk by an RCA sales engineer.  He had an anecdote about when he was testing a prototype of a counter MSI.  He finished wiring the test jig at the end of Friday, and started taking formal data Monday morning.  The device badly failed the clock rate spec.  It turned out that he had forgotten to turn on the power supply, and the input protection was passing the low-impedance pulse generator output to the bypassed power rail, which gave an insufficient Vdd for proper operation, but it still worked at low frequency.

[EECrAZY]

Probably not directly relevant to your device:
Back in the 1970s, when RCA introduced the 4000 series “COS-MOS” devices, I attended a talk by an RCA sales engineer.  He had an anecdote about when he was testing a prototype of a counter MSI.  He finished wiring the test jig at the end of Friday, and started taking formal data Monday morning.  The device badly failed the clock rate spec.  It turned out that he had forgotten to turn on the power supply, and the input protection was passing the low-impedance pulse generator output to the bypassed power rail, which gave an insufficient Vdd for proper operation, but it still worked at low frequency.

Funny, I had a very similar situation. +5V power was hooked up to the wrong pin but somehow it was still powering the IC through ESD diodes, output data was unusually noisy and one of the signals was missing (the one which was supposed to be generated by the miswired pin)