Hi. Here is an alternative (loop gain bode plot) sim. Using your values I get a phase margin of only 40 degrees with a 1mR source resistor, which explains the huge transient overshoot.
I'd be looking for either an alternative op-amp with a lower GBWP, or at perhaps implementing a discrete (bipolar transistor) driver stage with a significantly lower than 60 ohm Z-out between the OP07 and the mosfet gate, to push the "2nd" pole that is degrading your phase margin higher up in frequency.