It can't load anything else into the transmitter until what is there has been sent.
Oh yes it can

TXREG holds the next character to be transferred to the Transmit Shift Register (TSR) and TXIF is set whenever TXREG is empty. The TSR contains the character that is currently being transmitted.
So, the character in TSR is transmitting, the TXREG is empty and TXIF is set. You put a character in TXREG and it waits there for TSR to empty at which point TSR is loaded with the new character, TXREG becomes empty, TXIF is set again and you load TXREG with another character while the previous character is transmitting. The data flow is continuous and is proceeding almost as quickly as the hardware can allow.
In short. TXIF does not tell you that the transmission has finished, only that TXREG is empty.
To check for transmission complete you should test the TRMT bit of the TXSTA register. If TXIF is set and TRMT is set, only then is the transmission complete.
It is possible that your interface circuit needs a small recovery time between characters (some characters? Pairs of characters? I don't know, I just do SW

). The delay you are using allows for this, just testing TXIF does not.