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Comparator for restoring 27MHz clock from sine signal.

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Zero999:

--- Quote from: Esmund on February 18, 2019, 09:34:27 am ---
--- Quote from: Zero999 on February 15, 2019, 09:52:44 am ---
--- Quote from: DaJMasta on February 13, 2019, 04:32:55 pm ---I assume this is a sine centered around zero?  Well if it's just a sine, you already have your clock, you just have to make it usable by digital circuits, so:

signal -> DC blocking cap -> resistor divider to bias the signal to remain positive -> schmitt trigger/transistor amplifier/fast comparator -> regular, sharp edged digital clock signal
--- End quote ---
Yes, a couple of logic gates with feedback resistors will do that.


--- End quote ---

How about low input amplitude? I believe all logic gates like that have built in hysteresis loop, so I believe it won't be able to switch.

--- End quote ---
Ordinary logic inverters such as the 74AC04 don't have any built-in hysteresis loop, so it should work perfectly at low input amplitudes. A single non-inverting gate could be used but I suggested two inverting in series, simply because they're more common.

Here's an application note which goes through the calculations.
https://www.parallax.com/sites/default/files/downloads/AN015-SchmittTrigger-v1.0.pdf

Another useful link:
http://solarbotics.net/bftgu/tutorials_schmitt.html

Ian.M:
Doesn't the first inverter need negative feedback to keep it near its switching point?

Lets assume the output of the second one has railed (maybe transiently during startup).  Best case: the input cap will have charged so the first input is biased all the way to the same rail within 50us, and worst case could be under 20us.  Once the input's at the rail, a 100mv pk-pk input signal wont get it far enough off the rail to switch. Heck, assuming 80% logic '1' and 20% logic '0' thresholds, it wont even get it out of a valid logic '1' or '0' level!

iMo:
I was using this shaper with my reciprocal counter, and it worked nice (5/10MHz in my case).
The L1C1 at the input is tuned to the frequency, 27MHz in your case.
That amplifies the input sine, up to 4-5Vpp at the node "A" when lucky (because of the LC in resonance), moreover, it should lower the jitter as well.
After that LC a faster AHC14/AHC04 inverter could be used (ie the 5pin smd part).
The R2/R3 resistors create bias in the middle of the AHC14 schmitt-trigger range. The AHC04 should work as well.
The signal source should be low impedance.
Not tested in hw at 27MHz.

Zero999:

--- Quote from: Ian.M on February 18, 2019, 02:46:20 pm ---Doesn't the first inverter need negative feedback to keep it near its switching point?

Lets assume the output of the second one has railed (maybe transiently during startup).  Best case: the input cap will have charged so the first input is biased all the way to the same rail within 50us, and worst case could be under 20us.  Once the input's at the rail, a 100mv pk-pk input signal wont get it far enough off the rail to switch. Heck, assuming 80% logic '1' and 20% logic '0' thresholds, it wont even get it out of a valid logic '1' or '0' level!

--- End quote ---
You're right.  :palm:

I'm used to building this circuit with an input which is biased at approximately half the supply voltage. Anyway, this won't work with buffered gates. You need the unbuffered variety, otherwise adding negative feedback in the manner you've described, results in an oscillator. The supply current will also be very high. It's a bad idea.

Ian.M:

--- Quote from: Zero999 on February 18, 2019, 05:35:33 pm ---You're right.  :palm:

I'm used to building this circuit with an input which is biased at approximately half the supply voltage. Anyway, this won't work with buffered gates. You need the unbuffered variety, otherwise adding negative feedback in the manner you've described, results in an oscillator.

--- End quote ---
That needn't be a problem.  As long as the frequency of free oscillation is much lower than the input frequency, it will sweep the input bias through the switching point and lock onto the input frequency.  Depending on the time constants in the feedback loop it may take a time equivalent to a period or two of the free oscillation to stabilise.  See attached sim.  Whether or not you need to add extra logic to suppress the output till its locked to the input frequency depends on the application.


--- Quote ---The supply current will also be very high. It's a bad idea.

--- End quote ---
Maybe, but  as supply current for logic gates in transition is poorly specified - if at all - you wont know for certain till you suck it and see.

I agree its a lousy idea for production, unless you are prepared to qualify each batch of inverters for satisfactory operation and low enough supply current, but its entirely usable for one-offs and prototying - until you can get a more suitable fast comparator or limitng amplifier.

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