Author Topic: Concept of scalable n-bit comparator.  (Read 382 times)

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Offline KairatTopic starter

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Concept of scalable n-bit comparator.
« on: September 18, 2024, 07:30:56 am »
Greetings!

This is my first topic in this forum.
I want to share with you my concept of scalable n-bit comparator.
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Here CMN is my version bit comparator with function of 'suppression'. If input EN is 0, then all outputs set to 0.
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CMN structure.
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Example of 4-bit comparator.
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Note. Logic uses ‘suppression’ of next CMN blocks in chain when it determined which number A or B is greater.

This is my hobby to design binary logic. I didn’t test mentioned above logic on simulator yet. I just want to believe that it should work.
I would be grateful for your comments and notes!
« Last Edit: September 24, 2024, 02:57:14 am by Kairat »
 

Offline brucehoult

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Re: Concept of scalable n-bit comparator.
« Reply #1 on: September 18, 2024, 07:50:17 am »
Should work.

But it will have O(N) propagation delay.

A carry-lookahead adder (subtractor) has O(log(N)) propagation delay, and you can check signed & unsigned LT/GE ordering by looking at the carry out and top bit I think.

I figure a simple comparison that doesn't need the result of the subtraction should be no slower -- and use fewer gates.
 
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Online xvr

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Re: Concept of scalable n-bit comparator.
« Reply #2 on: September 23, 2024, 09:00:56 pm »
Reinventing the wheel may be useful (as brain exercise for example).
But if you need a result it will be better to use well known chips, like 74HC85 (4 bit, cascadeable)
 
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Offline KairatTopic starter

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Re: Concept of scalable n-bit comparator.
« Reply #3 on: September 24, 2024, 02:26:42 am »
Good morning!

Thanks for your advice! It's just my hobby (create logic and test it). Mostly I use Function Block Diagram for programming, so it's interesting for me to realize some common functions (like comparators, voting logics, etc.) in that environment by myself (for training purpose). To be honest, programming in FBD is more easy (I can just set desired execution order to blocks) rather try to create some logic in real hardware (I see that designer must take care about many physical factors, timing, etc.).
But, long time ago (already 10 years), I used to program PIC controllers, that was very interesting to create some devices on PCB.

Appreciate any comments and notes!
Best regards, Kairat.
 

Online xvr

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Re: Concept of scalable n-bit comparator.
« Reply #4 on: September 24, 2024, 09:24:18 am »
In a modern world PCBs with a sea of simple IC almost gone. Now digital hardware design is a something build from MCU, sensors, transievers etc. Logic used only as a glue leyer between them. If you want to design real hardware chemes, in a modern word it is a FPFA area.
 
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