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Confusing MOSFET transition times

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trobbins:

--- Quote from: mbless on July 14, 2020, 12:40:53 am ---This is the schematic based on the Brown 2002 paper which is a two-stage totem pole driver. I attached a screenshot of the 3D view, and the bottom is a solid ground plane. It's definitely not the best layout since the components are large and hard to minimize the loop area.
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I quickly checked your other thread, and same issue cropped up - why aren't you just using a purpose made gate driver IC - many varieties have been around for decades ?
If you are using that design because you read it in a book, then I think that is your problem.  Perhaps if you read up on the app notes for dedicated driver IC's, that may help you get a better awareness.

mbless:

--- Quote from: T3sl4co1l on July 14, 2020, 02:52:59 am ---Ugh... I was interested in this thread, but I see the forum attachment bug has rendered it useless. :palm:

Can you please host images externally for now?  (I recommend Imgur.)  Thanks.

Tim

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Does this work? https://imgur.com/a/AYe0QeD. Imgur has changed a lot since the last time I used it.



--- Quote from: trobbins on July 14, 2020, 04:21:12 am ---I quickly checked your other thread, and same issue cropped up - why aren't you just using a purpose made gate driver IC - many varieties have been around for decades ?

--- End quote ---
As addressed in that thread, it's a requirement to reproduce that topology as a baseline and then I can improve upon it. It's from a journal article with images of the PCB and output voltage. The PCB was etched and the components are fairly spaced out, so I'm not worried about my PCB layout. I'd wager I almost have the same dV/dt as them, so I'm trying to understand the mosfet difference here.

T3sl4co1l:
That works!

So, it looks that gate drive goes through quite a loop: C7, Q7, C9.  Probably 20nH total?  And if C9 is bypassing the supply with respect to the load side as well, then more than half of that loop is carrying load current as well as gate drive -- that is, you have source inductance through the whole path.

This is one of several reasons why the circuit shown is just not a good idea.

FYI, the gate capacitance doesn't make much difference; it's a small-signal off-state parameter (Vgs = 0) and ignores not just Miller effect, but much of the nonlinearity (Vds = 150V is well above the interesting 10-50V range for most of these).  Fortunately they're in order of Qg(tot) as well, so this should be okay.

What I think is interesting is:
- The times listed are in no proportion to the gate capacitance or charge
- The gate drive is pretty slow anyway; I've built a similar circuit (MOS inverter driver, though also buffered with a BJT follower) which seems to be much faster, even at high loads (10n + 2.2R):
https://www.seventransistorlabs.com/Images/GD8.jpg
https://www.seventransistorlabs.com/Images/GD9.jpg
- The FQP and FQA parts have serious ringing, at turn-on at least.  Their capacitance is high enough that there's a modest Q to the inductive loop.  Which if that's ballpark 4nF and 20nH would be 18MHz, or a 28ns half-period.  Which... is eerily close to the lumps seen on the FQA gate waveform, despite my just ramming together two one-would-hope unrelated parameters.
- In here,
--- End quote ---
I think your Miller plateau is actually very near the top, and doesn't start until about the 25ns mark.  Where the crazy stuff (over/undershoot) begins.  That this is at a high voltage, implies one or both of: drain current is very high, or source inductance * dI/dt is very high.
- Likewise, everything starts unloading by the ~113ns mark, and you get similar ringing, but at somewhat higher frequencies because the gate capacitance is now higher (because Vds is high).

So we might express this as so:

Hypothesis: gate charge dominates switching time.
Evidence: test a series of transistors with a 5:1 spread of gate charge; examine switching time.
Result: switching time has a 2:1 spread, and is poorly if at all correlated with gate charge.
Conclusion: the hypothesis is very unlikely to be true.

Indeed, we might suspect that, because the switching time has barely changed over this spread, we should consider other invariants in the circuit.

The drivers are one.  You can test them independently, with a low inductance RC network, say, 1-4.7nF + 1R.  You should find they perform well, and that the variance is smaller than seen here -- it might span say 10 to 20ns, or be even faster like 5-10ns.  If it's 10-20ns, it may be a strong contributor to overall performance; if it's much shorter, you'll be looking elsewhere.

I think you will find the elephant on this PCB (so to speak) is the switching loop.  Make gate drive through a short Kelvin connection, and you will get much closer to the capability of the driver.  This isn't easy to deliver via coupling capacitors.  I suggest building an isolated gate driver, so you can continue experimenting with greater flexibility.

I think it's telling, that the gate waveforms are already at full, in the first 15ns or so rising, and 10ns falling; the transistors are literally catching up afterwards.  And a slower rise is typical of "complementary" PMOS, so I suspect the driver is doing alright for what it is.

Also, if possible, change the package:
- D2PAK parts have shorter lead length
- Or especially D2PAK-multilead types, with intended Kelvin connections
- DFNs, if possible.  Not really an option, I think, as PDSO-8 style parts don't come in quite high enough ratings.  Also, the real good ones are GaN, which might be... a bit too hot to work with, without more experience.  (Something to look forward to?  Just blast out 1ns edges in the first place? :-DD )

SMTs are harder to heatsink than THT; and DFNs are harder than D2PAKs.  If your PRF is high enough to require substantial heatsinking, this might not be an option.  In that case, you can consider using more THTs in parallel (with individual drivers, to avoid strays causing skew), which reduces lead inductance proportionally, but increases heatsinking capacitance proportionally as well.

Which, if you get to the point where heatsink capacitance is a barrier, they actually make HIP extruded alumina heatsinks -- sounds insane but they're not even aerospace priced, very much affordable in one-offs.  Thermal conductivity is a lot poorer than aluminum of course, but still more than good enough for natural convection, or modest forced convection.  As an excellent insulator, they add almost no capacitance to the drain tab!

And if you do need a lot of power, look at AlN insulators -- fantastic stuff, conductivity about halfway between aluminum and copper metal!  A bit hard to source.

Tim

magic:

--- Quote from: mbless on July 14, 2020, 12:40:53 am ---This is the schematic based on the Brown 2002 paper which is a two-stage totem pole driver. I attached a screenshot of the 3D view, and the bottom is a solid ground plane.
--- End quote ---
Nitpick: totem pole is a pair of emitter/source followers, like your first two FETs driven by the opamp. The other "stacks" are basically discrete CMOS inverters.

But why? That thing looks complex for what it does. Why drop money on a high speed opamp if there are much simpler gate drivers which, I think, should be able to do the job better and probably even cost less?

From my time playing with high speed switching, I remember TC4551 being the beefiest driver I found (chances are a weaker/cheaper one would suffice for you). I ended up not using this part, but anyway, look at the datasheet - it laughs at load capacitances below 1000pF. It should get to the Miller plateau in less than 10ns and then plow through it at up to a few amps of current, limited by the FET's gate resistance and your board's inductance, which you minimize by placing things close together and using a single-chip driver kinda makes that easier.

I think even replacing the opamp with a gate driver and then using the discrete output stage would still be an improvement, in terms of cost if nothing else.


--- Quote from: mbless on July 14, 2020, 12:40:53 am ---It's definitely not the best layout since the components are large and hard to minimize the loop area.

I also added the gate drive voltage traces. All except the STF12N50M2 initially reach the peak drive voltage before dropping. Is that the oscillations you speak of?

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The peaks and valleys are probably a slight ringing due to all inductance between the driver and the FET.
You really need to minimize these loops:
gate - gate driver output - gate driver guts - gate driver ground - source
gate - gate driver output - gate driver guts - gate driver VCC - gate driver bypass capacitor - gate driver ground - source

This also implies that you need a nearby bypass capacitor between the driver's ground and the FET's source, if you really insist on AC coupling between the driver and the FET. I would investigate the feasibility of putting the driver at -350V and somehow isolating its input signal, perhaps?

If you want to AC couple the driver's output, put it as close to the FET as HV clearences permit. And I think a smaller, ceramic coupling capacitor would have less ESL, not sure if there are some safety concerns preventing that.


--- Quote from: mbless on July 14, 2020, 01:17:34 am ---Are you sure you looked at the correct datasheets? At 150V I'm seeing 30pF for STF12N50M2, 18pF for IPA60R280P7S, ~100pF for FQPF8N80C, and ~250pF for FQA19N60.

--- End quote ---
There is actually one place where output capacitance matters: the end of the falling/(rising?)::) AKA the turn-off edge. Since the output is pulled up to 0V by a resistor, it's subject to the standard exponential decay curve. The knee near 0V is probably due to differences in output capacitance and nothing more. 250pF times 25Ω is 6ns time constant - even if the FET conducts exactly nothing, it takes 6ns for the output voltage to get some 60% closer to 0V than it currently is, again and again. Use the FET with the lowest output capacitance if this is important to you, simple as that.

edit
Miller plateau is when the drain voltage rises/falls and your switching speed is limited by your ability to source/sink current into the parasitic gate-drain capacitance which is being (dis)charged in the process.

BTW, look up maximum dV/dt that your FETs are capable of surviving and (ideally ;)) don't exceed this limit. There is such a limit, if you go faster, the FET may spuriously turn-on when it's supposed to be off and blow up. I have never seen it happen (because I didn't try), but all FET manufacturers swear that it can happen.

T3sl4co1l:
Oh, I was also thinking but forgot to add: tabulate Vgs(th), and maybe transconductance at a given (equal for all parts if possible) drain current.

The Miller step is relative to Vgs(th), so a higher threshold gives slower rise and faster fall; or vice versa.  (A good reason to avoid logic-level parts, when full drive voltage is available -- the Miller step is at so low a voltage, you literally can't draw any more than whatever the short-circuit current is from the gate.  Only fix then is to use negative turn-off.  Which is definitely an option here, given the cap coupling, heh...)

Tim

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