Electronics > Projects, Designs, and Technical Stuff
Confusing MOSFET transition times
mbless:
--- Quote from: T3sl4co1l on July 14, 2020, 06:21:05 am ---- The FQP and FQA parts have serious ringing, at turn-on at least. Their capacitance is high enough that there's a modest Q to the inductive loop. Which if that's ballpark 4nF and 20nH would be 18MHz, or a 28ns half-period. Which... is eerily close to the lumps seen on the FQA gate waveform, despite my just ramming together two one-would-hope unrelated parameters.
- In here, I think your Miller plateau is actually very near the top, and doesn't start until about the 25ns mark. Where the crazy stuff (over/undershoot) begins. That this is at a high voltage, implies one or both of: drain current is very high, or source inductance * dI/dt is very high.
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Now that's some interesting guess work! I calculated 48MHz for FQP and 30MHz for FQA. What makes you think the Miller plateau is at 10-12V instead of ~6V from the datasheets? Comparing the gate voltage and Vds waveforms shows it is around 10-12V.
--- Quote from: T3sl4co1l on July 14, 2020, 06:21:05 am ---I think you will find the elephant on this PCB (so to speak) is the switching loop. Make gate drive through a short Kelvin connection, and you will get much closer to the capability of the driver. This isn't easy to deliver via coupling capacitors. I suggest building an isolated gate driver, so you can continue experimenting with greater flexibility.
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I do have an isolated gate driver PCB with the desired small loop area to test out. It appears the general consensus is to use the ideal PCB to test the mosfets :palm:
--- Quote from: T3sl4co1l on July 14, 2020, 06:21:05 am ---Also, if possible, change the package:
- D2PAK parts have shorter lead length
- Or especially D2PAK-multilead types, with intended Kelvin connections
- DFNs, if possible. Not really an option, I think, as PDSO-8 style parts don't come in quite high enough ratings. Also, the real good ones are GaN, which might be... a bit too hot to work with, without more experience. (Something to look forward to? Just blast out 1ns edges in the first place? :-DD )
SMTs are harder to heatsink than THT; and DFNs are harder than D2PAKs. If your PRF is high enough to require substantial heatsinking, this might not be an option. In that case, you can consider using more THTs in parallel (with individual drivers, to avoid strays causing skew), which reduces lead inductance proportionally, but increases heatsinking capacitance proportionally as well.
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I actually have DPAK versions of a couple of the mosfets in the same PCB design to see if I measure the effect of lead inductance/package size. The PRF is very low, so I'm not expecting to need heatsinking.
--- Quote from: T3sl4co1l on July 14, 2020, 06:57:39 am ---Oh, I was also thinking but forgot to add: tabulate Vgs(th), and maybe transconductance at a given (equal for all parts if possible) drain current.
The Miller step is relative to Vgs(th), so a higher threshold gives slower rise and faster fall; or vice versa. (A good reason to avoid logic-level parts, when full drive voltage is available -- the Miller step is at so low a voltage, you literally can't draw any more than whatever the short-circuit current is from the gate. Only fix then is to use negative turn-off. Which is definitely an option here, given the cap coupling, heh...)
Tim
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That's a good tip since I need to improve on the falling edge. :-+
temperance:
Drain source capacitance for your MOSFET's
STF12N50: 4nF @ 100mV and 1nF @ 10VV
IPA60R280: 10nF @ ~0V and 200pF @ 25V
FQPF8N80: 2nF @ 100mV and 250pF @ 10V
FQA19N60: 5nF @ 100mV and 500pF @ 10V
The drain to source waveform shows how the voltage dependent drain source capacitance is being charged by a 50R source. That's why the IPA60R280 is "slowest" is your setup.
And other thing I forgot to mention about the falling edge (drain to source) but it has been mentioned by others is the intrinsic gate resistance which is very often not included in the data-sheet.
You might want to read this book. Especially chapter 3.2:
https://archive.org/details/bitsavers_siliconixdixMOSPOWERApplications_38092918
mbless:
--- Quote from: magic on July 14, 2020, 06:35:39 am ---This also implies that you need a nearby bypass capacitor between the driver's ground and the FET's source, if you really insist on AC coupling between the driver and the FET. I would investigate the feasibility of putting the driver at -350V and somehow isolating its input signal, perhaps?
If you want to AC couple the driver's output, put it as close to the FET as HV clearences permit. And I think a smaller, ceramic coupling capacitor would have less ESL, not sure if there are some safety concerns preventing that.
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I also have an isolated gate driver PCB using recent tech to test. The attempt at AC coupling was quite simple but appears to be hard to implement in terms of loop current. I think I would have clearance issues for 500V, of course that all depends on which standard you follow for clearance and creepage. I'm also not sure of typical ceramic caps' quality at 500V.
--- Quote from: magic on July 14, 2020, 06:35:39 am ---
--- Quote from: mbless on July 14, 2020, 01:17:34 am ---Are you sure you looked at the correct datasheets? At 150V I'm seeing 30pF for STF12N50M2, 18pF for IPA60R280P7S, ~100pF for FQPF8N80C, and ~250pF for FQA19N60.
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There is actually one place where output capacitance matters: the end of the falling/(rising?)::) AKA the turn-off edge. Since the output is pulled up to 0V by a resistor, it's subject to the standard exponential decay curve. The knee near 0V is probably due to differences in output capacitance and nothing more. 250pF times 25Ω is 6ns time constant - even if the FET conducts exactly nothing, it takes 6ns for the output voltage to get some 60% closer to 0V than it currently is, again and again. Use the FET with the lowest output capacitance if this is important to you, simple as that.
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I would expect to see a more pronounced knee for FQP than STF since it has higher output capacitance, so there must be more going on. Or my eyes are deceiving me.
--- Quote from: magic on July 14, 2020, 06:35:39 am ---BTW, look up maximum dV/dt that your FETs are capable of surviving and (ideally ;)) don't exceed this limit. There is such a limit, if you go faster, the FET may spuriously turn-on when it's supposed to be off and blow up. I have never seen it happen (because I didn't try), but all FET manufacturers swear that it can happen.
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Good point. I'm seeing 50-80 V/ns, so I'm getting close to that at peak dV/dt during turn on. I can foresee surpassing that when I go to higher voltages.
--- Quote from: magic on July 14, 2020, 07:14:39 am ---OP actually AC couples the drive signal so I think the drive waveform will be centered around ground or something like that?
In such case, a low threshold / logic lever FET could even offer better on/off matching, I think.
That being, the gate waveforms that have been posted show a 0V-15V swing. What's going on in here? :wtf:
edit
Nevermind, the output is at zero almost all the time and only turns on for 100ns. So it will be 0-15V swing and 7V threshold FET would be ideal. Note that it may be easier to change driver supply voltage than use an otherwise bad FET just for its threshold voltage.
And that's provided that the output impedance / current capability of your driver is fully symmetric :D
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Correct, the mosfet gate is actually swings from -150V (off) to -138V (on). I didn't include the plot since I stupidly recorded data with it in dc-coupled mode, so the bit digitization resulted in poor resolution. It looks the same, though, with ringing in FQP and FQA parts. There's also ~3V peak loss.
mbless:
--- Quote from: David Hess on July 14, 2020, 01:05:34 pm ---Are you separating delay time and transition time? During turn-on, until the gate voltage reaches the gate threshold voltage, nothing happens so there is a delay before the MOSFET begins to turn-on. Transition time is only controlled by the charge transferred during the Miller plateau. The same thing applies during turn-off with the delay being proportional to the gate voltage above the Miller plateau.
Some designs minimize the turn-on and turn-off delay by precharging the gate or limiting how much extra charge is applied. But when PWM is used, then the extra delay times get removed by the PWM control circuits so they do not matter.
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Yes, that is visible in the plots as the x-axis is relative to the input signal. The gate voltage starts to rise around 10ns, but the output voltage doesn't change until 20-30ns when the gate voltage is 5-11V. I'm not concerned with delay time since I'll be running low PRF, and it is low enough for my application.
mbless:
--- Quote from: temperance on July 14, 2020, 01:22:59 pm ---Drain source capacitance for your MOSFET's
STF12N50: 4nF @ 100mV and 1nF @ 10VV
IPA60R280: 10nF @ ~0V and 200pF @ 25V
FQPF8N80: 2nF @ 100mV and 250pF @ 10V
FQA19N60: 5nF @ 100mV and 500pF @ 10V
The drain to source waveform shows how the voltage dependent drain source capacitance is being charged by a 50R source. That's why the IPA60R280 is "slowest" is your setup.
And other thing I forgot to mention about the falling edge (drain to source) but it has been mentioned by others is the intrinsic gate resistance which is very often not included in the data-sheet.
You might want to read this book. Especially chapter 3.2:
https://archive.org/details/bitsavers_siliconixdixMOSPOWERApplications_38092918
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I see it now! I needed to look at the output capacitance when it's on (Vds=0). Those numbers fit the turn-off trend well. And thanks for the reference material.
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