Electronics > Projects, Designs, and Technical Stuff
Confusing MOSFET transition times
magic:
--- Quote from: mbless on July 14, 2020, 01:09:07 pm ---Now that's some interesting guess work! I calculated 48MHz for FQP and 30MHz for FQA. What makes you think the Miller plateau is at 10-12V instead of ~6V from the datasheets?
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Remember that the voltage you see is not the "true" gate voltage but the voltage you applied to the outside end of a 7Ω parasitic resistor.
If you add another 70Ω externally, you will probably be able to see something resembling the datasheet waveform on the transistor's pin.
--- Quote from: mbless on July 14, 2020, 01:32:05 pm ---I would expect to see a more pronounced knee for FQP than STF since it has higher output capacitance, so there must be more going on. Or my eyes are deceiving me.
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Fact. But as I said, time constant is only some 6ns so perhaps it fits. You can see more of this effect on the high capacitance FQA, and I would say that the low capacitance Infineon part actually shows the most promising performance on average, except for the problematic bottom knee (top is actually quite nice).
It also occurred to me that there is another issue: capacitance increases dramatically at low Vds, which causes a soft knee at the bottom end on both turn-on and turn-off edges. That being said, this effect alone would make the two edges mirror images of each other but the turn-off edge is much worse. It might be due to gate ringing aligning differently with each edge.
In the future, it would be helpful if you posted the plots differently: Vgs and Vds of each FET overlaid on one image. That makes them easier to correlate and see what's going on.
Perhaps the sharper top knee of FQP has something to do with the gate dipping down to -1V at about the same time?
You should do the math and see if those curves fit the RC curve expected, or are worse, or (if such a thing is even possible) better.
T3sl4co1l:
Note that I already cheated in just such an overestimate -- on the FQA, I went with 4nF because Ciss is about 2nF at high voltage and typically about doubles at low voltage (i.e., in saturation, when turned on). This forms a resonant tank between supply bypass cap, gate driver (which is a bit of resistance, and not much else), coupling cap and transistor, and the strays of all of these, and the PCB.
It sounds accidental, but this is part of the actual circuit, and so it's not as much of an accident as it seems, that I put those two numbers together and got such good agreement. :)
It's pretty scary actually, to have a loop like that, as part of the load supply. What happens if there's a load or source transient of more than a few volts? Pfsst...BANG!
With a direct driver, the drive loop inductance can be much smaller, and most importantly, the mutual (shared) inductance between driver and load goes to single digits -- dI/dt will be much higher, and Miller plateau will look as expected.
And yes, that's the real Miller plateau I think -- you can also confirm it in a simulation with source degeneration inductance.
Relevant story: I've made a converter that runs at 12V 20A, and used a current shunt resistor that added about 10nH to the ground return path -- even with beefy driver ICs and confirmed 20ns edges at the gate pins, the switching was still some slow 50ns or thereabouts, because it was entirely dI/dt limited. In the same way that you make a current source by putting resistance in the source return path, you make a ramp source by putting inductance in the source return path. Inductance kills, when it comes to switching!
Tim
temperance:
Note that the miller plateau might not be visible or very hard to see at turn off because the drain voltage starts to rise much later because of the RC time constant. (50R with Coss) At turn, it should be very easy to see.
Ringing in the gate driver can be solved by placing a ferrite bead + a small resistor in series with the gate. Something like this will work:
https://www.we-online.com/catalog/datasheet/742792620.pdf
temperance:
--- Quote from: T3sl4co1l on July 14, 2020, 03:17:07 pm ---
And yes, that's the real Miller plateau I think -- you can also confirm it in a simulation with source degeneration inductance.
Tim
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That's not the miller plateau. The miller plateau can only be observed at the gate. But at turn off, you want see to much because Coss is being charged trough a 50R resistor.
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