Connecting different grounds in mixed analog and digital circuit

[prasimix]

For stability testing, the critical tests for voltage regulation are:
Sinulations should include realistic parasitic inductance for the shunt / GND path (here maybe 50 nH).
The voltage set to do the test should not make a difference with this circuit. Usually the extremes are worst.
1) just a current souce (Spice part), as load. DC current near 0 + AC Current -> effectively look at output impedance
2) same as before, but higher current (e.g. 2/3 of max.)
    The output impedance should not have any phase shift larger than +-180 deg.
    For the range around 1 MHz, adjustung the output capacitor and possible series resistor might help

This 2 test can test most cases of instability. Idleally one wants a low impedance and enough distance to the +-180 deg. bounds, at least where impedance is not very low. So getting very close (e.g. 175 deg.) at something like 100 Hz is normal, but the 100 kHz - 10 MHz range should have much more reserve (e.g. > 30 deg).  However there may still be poor regulation - especially if one only looks to frequency domain and trys to defeet causality by adding more and more RC combinations.

So the final test is in time domain:
3) Testload of pure cap + current source with steps of something line 10 mA / 1 A and back with something like 1 µs rise/fall
    Caps at something like 10µF , 100µF, 1000µF and 10000µF with low or 0 ESR and possible realistic values.
    Quite some ringing at 10 mF (or more)  and 0 ESR is more or less normal. Just a few mohms of ESR

Thanks Kleinstein. I realize that in fact my question is off-topic and that will be better to continue with such discussion in the main thread. I expected some real-world testing and I'll definitely will need some further assistance how to conduct proposed tests (both as simulation and in real world ).

[prasimix]

Ground plane looks good.  Some routing tips:

Observe the negative space, which is filled by the pour.  Try to have it wrap around every trace (or grouping of traces) if possible.  Examples (pour has been colored cyan for clarity):



On the bottom left, these are a good example.  The ground fill keeps the traces isolated, and somewhat reduces their impedance / inductance (if this is useful).  Downside: takes up a lot of space, so it's not so handy to do for a bunch of signals at a time (say, a parallel data bus?).



Here's a tiny hiccup, of sorts.  If the via can be moved, allowing the pour to close around the pads, you might as well.  The loop in this case isn't very big (the peninsula is only a cm or two long), so it won't be "flapping around" with much inductance, certainly not enough to notice in a circuit like this.  These kinds of details get more important in switching or precision or RF, so it's a practice-makes-perfect sort of thing to be prepared when/if you do work on such circuits.



Where you have a bunch of traces, it can be handy to group them, or hug along routes -- but mind that, in doing so, you trap and isolate the pour where the traces gather.  If there isn't much advantage to gathering traces, say over a short run, you might as well give more clearance to everything, so the ground can fill.  A possible re-route is shown in red.

Remember that every trace is cutting a slot into the pour.  Around this trace, there may be slightly different voltages on the left/outside and right/inside bits of pour.  You could fix this with a hack, by adding a two vias and a short trace to jumper over this splitting trace, or better still, stitch it with top side pour wherever possible.

Tim

Yes, its much better when more pairs of eyes looks into it. I spent so many hours that I became temporarily blind to red and blue (and yellow).
I'll add on few places mentioned hack with vias since that seems better then top side pour, or maybe not. I have to check that (does not cost a lot to try).

[prasimix]

hi Tim, here are some replies to your recent review:

FYI, Q4 gate is coming out the wrong side (note on Q1, it's drawn exiting from the source side). 

Yes, thats strange. I used some existing devices from Eagle library where PMOS symbol was not correct. I've fixed that by creating my own device.

Also, BSS84 would be more traditional there, though it won't make any difference if you don't mind the extra capacity of the IRLML2246.

True, it's used on another PCB that belongs to this project and I just copy and paste it. It's overkill here and can be replaced with i.e. BSS84.

If you want a more accurate near-zero threshold for IC4, you can replace R53 with a pair of resistors to GND.  This anchors the middle of the divider (indeed, splits it into two separate dividers), so that ratio differences in R50/R55 have less effect.

Already done. I tried to save one THT resistor place on the PCB in the past but now that is completely pointless.

Also, the output resistors as chosen (R48, R49, R54, R56) are such that D12, D13 don't do anything.  The diodes might be relevant if the supplies come up at different rates (though, within ratings, the MOSFETs will never be in danger).  Or if you want to make use of them, it would be perfectly fine to reduce the resistor ratios, so that the diodes become forward biased while the comparators are on.  Really doesn't matter, it's very mildly redundant.    (I guess what I'm feeling, philosophically, is: if you have the choice between two nearly equivalent options, you must be near -- but not on -- a local minima; this is a sign that you perhaps should rethink the thing, until you find an even better local (perhaps even global) minima.  At least, when it's something that's actually worth the work.)

That was also something that was really old and as you said D12 and D13 doesn't make sense. With replacing +/-15V with +5/-5V rail supply it should looks like this:

Which segues into the other filter thing: the shunt sense IC3 should have some filtering on its inputs.  This is a bipolar op-amp, at very small signal levels, so it will be doubly important to keep HF noise (anything over perhaps 500kHz) well away from it.  R35, R38 are also rather low values, which are something of a fault hazard to IC3 -- short circuit current through the shunt can deliver quite a bit of current into the IC's input protection diodes.  I'd suggest >100 ohms, perhaps split in half (2 x 51 ohm each?) with a 4.7nF to ground (in the middle) for filtering.

I put that in the latest revision of the PCB. Using small resistors was inspired by some schematic of current monitor mentioned in LTC2057 datasheet (pg.23).

Going back to IC1 and IC2, it seems rather odd to use +/-15V supplies, yet use only about the -2 to 0V range.  You should use only as much as needed, so the outputs don't have to slew so far when they go into the linear range.  This reduces integrator windup, which is a significant limitation on the speed of this type of control circuit.  Simple solution is to increase R24 and/or R18 dramatically, so the gain is lower and the useful op-amp range is wider.

Alternately, you could rewrite much of the circuit to use, say, +/-5V supplies (which would eliminate one supply), and use a R2R type amp like TLV2372.

Why +/-15V is still here I really cannot remember. It was required for some of the first version and when I decide to make adaptation of Liv's circuit where +/-5V is also used, its really don't need to be here anymore. Especially because stepping down with existing pre-regulator where bias supply is located should not be a problem at all.
 

The Q4 pulldown stuff seems odd (it's like Q1 and Q4 act as a complementary source follower pair), but I guess it's really only being used as a turn-off discharge.  Beware that it won't operate very happily if you were charging a battery pack then hit the "disable" switch!  (That said, 50V maximum and ~0.3A limit suggests a modest 16W maximum dissipation, which is fine for a TO-220 MOSFET like that.  As long as you have the load current displayed, the user will be able to see their battery charge being pissed away, too. )

That is a so-called "down-programmer" (DP). It helps to set faster new value that is lower then current one. DP as OE will be controlled by MCU and mentioned scenario will not be allowed. But, controlled battery discharge will be one of the possible scenario. If someone like to use post-regulator without MCU board it simply has to connect OE and DP switches in serial:

[Kleinstein]

The down-programmer may also help to have some bias current, so that the output stage is not starting to operate from idle. This helps to get a fast and stable regulation, as the parameters of the output stage don't change that much. So having a minimum current from the down programmer will likely alow for a faster response. So the option to turn of den DP is two sided.
However it migher be neccesary to replace the 6.2 V zener diode with something adjustable, as to control the idle current and compensate for varying U_GS of the MOSFETS.

However the downprogrammer looks relatively complicated compared to a classic complementary follower.

For those who want to charge batteries, just add a second output with diode and fuse, specially for charging. This might save the circuit in case of reversed voltage.

In checking stability from output impedance, the limits are no more than +-90 deg. of phase shif of cause, thus something like a passive load.

I did a quick simulation of the circuit - though with some parts exchanged to types where LTspice has models. It looks generally Ok, if C15 (extra FB to voltage regulator) is removed. Input to the differential amplifier can be simplified to 1 cap each.

[T3sl4co1l]

I put that in the latest revision of the PCB. Using small resistors was inspired by some schematic of current monitor mentioned in LTC2057 datasheet (pg.23).

Of course, you aren't using an LTC2057, and you aren't using the same circuit type either.   I think they just did that for brevity: to get a ~1k load on the output (so the diode works, if present), they need a 1k feedback network.  Which needs 10 ohm resistors for a gain of ~100 (well, 101).  The other resistor (to +in) I think is just a formality, i.e., you always want similar or equal Thevenin resistances to both inputs, so that input bias current (which is likely to be equal when everything is settled in equilibrium) doesn't induce an offset.

Which is a funny example, because with <1nA of bias, 10 ohms will produce <10nV of offset, well below Vos, and down in the noise floor where you may not be able to see it at all (over any time scale, because 1/f noise directly interferes with DC measurements).

Now, it is worth noting that some current sensors do find this very important.  The AD8210 current sense amplifier exhibits a large input bias current when the inputs are somewhere below VCC.  It also has a high voltage tolerance, so it's fine to have the inputs riding well above VCC, and it's just fine to connect it directly to a power rail (high side current sense).  It's a very special kind of differential amplifier.  Most general purpose diff amps won't be so inviting, and you need traditional precautions.

Why +/-15V is still here I really cannot remember. It was required for some of the first version and when I decide to make adaptation of Liv's circuit where +/-5V is also used, its really don't need to be here anymore. Especially because stepping down with existing pre-regulator where bias supply is located should not be a problem at all.

Cool, that'll probably save a fraction of a watt besides (hey, it's something?).  Always nice to cut down the number of supply rails needed.
 
Cheers,

Tim

[prasimix]

Here is the latest revision where two previous input power connectors are merged into single one. The voltage reference is also moved up.



Ground plane is now looking like this:



Some manufactures recommend that ground plane should be omitted with certain op-amps due to possible negative effect of stray capacitance. Don't know if such thing is applicable here. If that is the case, a "star-ground" in top half can be still created.

I'd also like to hear your opinion about ground on the pre-regulator PCB which (schematic is in the attachment) looks like this:



On the bottom layer I connect ground return to the bulk capacitor minus terminal (that is not the case if three smaller capacitors is used to have better ripple current figure):

[prasimix]

I did a quick simulation of the circuit - though with some parts exchanged to types where LTspice has models. It looks generally Ok, if C15 (extra FB to voltage regulator) is removed. Input to the differential amplifier can be simplified to 1 cap each.

Hi Kleinstein, please let me know what did you find out about C15. How it affects the whole circuit?

[prasimix]

Why +/-15V is still here I really cannot remember. It was required for some of the first version and when I decide to make adaptation of Liv's circuit where +/-5V is also used, its really don't need to be here anymore. Especially because stepping down with existing pre-regulator where bias supply is located should not be a problem at all.

Cool, that'll probably save a fraction of a watt besides (hey, it's something?).  Always nice to cut down the number of supply rails needed.

There is a still one possible obstacle to move from +/-15V to +/-5V. Down-programmer circuit require negative voltage which has to be a little bit over -5V or logic level p-ch mosfet for Q5 has to be used. Unfortunately it seems that such device is a rare animal in TO-220 package and at least -55V. Until now I found just a few: IRF's IRLIB9343 or Vishay's SUP53P06-20 and SUP90P06-09L. Another possibility is to extend input power connector for another two pins and bring -8V from pre-regulator that is used for -5V LDO.

[T3sl4co1l]

There is a still one possible obstacle to move from +/-15V to +/-5V. Down-programmer circuit require negative voltage which has to be a little bit over -5V or logic level p-ch mosfet for Q5 has to be used. Unfortunately it seems that such device is a rare animal in TO-220 package and at least -55V. Until now I found just a few: IRF's IRLIB9343 or Vishay's SUP53P06-20 and SUP90P06-09L. Another possibility is to extend input power connector for another two pins and bring -8V from pre-regulator that is used for -5V LDO.

Ah, but it's not hard switching, is it?  And it doesn't much matter if it does, as long as it's able to pull the output reasonably low with enough current (100mA? amperes?).  All of these seem to be overly large, in fact!  Though you might have to simply roll with it, to get the power dissipation.

I'd avoid the IRF part: just at first glance, Vgs(th) is not in a guaranteed range, and that's no good for a linear or semi-linear sort of application.  The SUP53 seems nice, and is also guaranteed for switching at Vgs = -4.5V, so you know without a doubt it's more than overkill.  The '90 is most likely a scaled up version, so unless you need the sheer switching capacity, you're just paying more for no benefit.  You can probably go much smaller, if availability and dissipation are still there.

Board layout looks generally good.  You've got good conservation of ground continuity and all that, I see more use of vias, and the main current paths are either routed closely, or bypassed nearby (in the case of the power supplies).

A note: I see the ground "jumpers" you've placed, but they're used a little inconsistently: that is, the longest bottom side trace has one jumper over it, splitting it into two spans...which in turn still have lengths several times of any other slots!

If you are limited to one jumper, placing it towards the middle is probably the best idea (which I think has been followed), but if not limited -- the more, the merrier.

The purpose is partly to address the inductance (or the RF resonances) of the slots, but equivalently as well, the sources that might induce currents into those slots -- namely, any top side traces crossing them.  To keep current loops smallest, the jumper(s) should be placed alongside the most sensitive, noisy or high-power traces that cross the slot.  So you're not only shorting across the slot (making it a shorter electrical length), but providing a current path, directly where it's needed, preventing that offending current from inducing currents elsewhere in the first place.

I'd also suggest using wider copper (in most cases I think you have enough space to go at, say, the via OD?), since the main hazard to a power supply application will be low impedance ground loop currents, and a thin trace isn't much better than a slotted pour, even if it's pretty deep.

 

Tim

[Kleinstein]

If negative supply for the down programmer is a real problem, one could also change vom a PMOS to a PNP. Something like a MJE15029, (BD140 is rather low in maximum power) might be an option - just the zener diode needs to be adjusted to a lower voltage. At least resonable fast PNPs are relatively easy to get, and U_BE is lower and rather well defined.


I did a few more simulations (much of it just variations of the output stage):

In the regulator C15 (old numbering) is usually just causing trouble -  the best results where whithout it. This is also clear, as it trys (not working this way anyway) to compensate for the drop at the shunt at high frequencies. However having the shunt and thus some resistive part is actually very good at high frequencies - this one known way to stabilize with capacitive loads.

With a MOSFET output stage it's really a bad idea to run without or a low bias current. At low currents MOSFETS get much slower than they are at high currents. So the in principle fast MOSFET looses it's advantage over a BJT power stage. Without any bias through the downprogrammer the loop would have to be tuned really slow - thus resulting in rather poor regulation or instability at low volatges (current throug resistors goes down).  BJT also tend to get slower at low currents, but the effect seems to be not that strong. So a BJT power stage miight run with lower bias - though the driving stage will need more power, so the savings may not be large.

So I really see no use i turning the down-programmer off - the regulator is just not working well without it. If really needed an extra optional diode at the output might be an option that causes less trouble to regulation - in this case one might have the option to have a slow regulation only at low currents, getting resonable fast if more than some 100 mA are used. Having something like 100mA bias may mean up to 4 W of waste heat - not good, but still viable mains powered.

If no need to turn the down programmer off, the output stage could be simplified a little, using less diodes etc.

[prasimix]

So I really see no use i turning the down-programmer off - the regulator is just not working well without it. If really needed an extra optional diode at the output might be an option that causes less trouble to regulation - in this case one might have the option to have a slow regulation only at low currents, getting resonable fast if more than some 100 mA are used. Having something like 100mA bias may mean up to 4 W of waste heat - not good, but still viable mains powered.

If no need to turn the down programmer off, the output stage could be simplified a little, using less diodes etc.

You're right. Down-programmer (DP) should be active most of the time. There is two possible scenarios for switching if off independently of Output enable (OE) control: one is when charging a battery. Another is when two channels are connected in parallel. It seems that is better to have only one DP active.

[prasimix]

There is a still one possible obstacle to move from +/-15V to +/-5V. Down-programmer circuit require negative voltage which has to be a little bit over -5V or logic level p-ch mosfet for Q5 has to be used. Unfortunately it seems that such device is a rare animal in TO-220 package and at least -55V. Until now I found just a few: IRF's IRLIB9343 or Vishay's SUP53P06-20 and SUP90P06-09L. Another possibility is to extend input power connector for another two pins and bring -8V from pre-regulator that is used for -5V LDO.

Ah, but it's not hard switching, is it?  And it doesn't much matter if it does, as long as it's able to pull the output reasonably low with enough current (100mA? amperes?).  All of these seem to be overly large, in fact!  Though you might have to simply roll with it, to get the power dissipation.

I'd avoid the IRF part: just at first glance, Vgs(th) is not in a guaranteed range, and that's no good for a linear or semi-linear sort of application.  The SUP53 seems nice, and is also guaranteed for switching at Vgs = -4.5V, so you know without a doubt it's more than overkill.  The '90 is most likely a scaled up version, so unless you need the sheer switching capacity, you're just paying more for no benefit.  You can probably go much smaller, if availability and dissipation are still there.

I decide to extend input power connector. In that way I can bring -9V from pre-regulator to DP and don't narrow a mosfet selection to the few "exotic" devices.

[Kleinstein]

The bias current of the MOSFET influences the regulator speed - possibly down to near 0. So there needs to be some bias current even if only in the sub mA range. The current plan may need even more, as at currents below about 1 mA R33 will bypass the MOSFET. At volatges above 5 V this might be just one of the dividers at the output - but this does not work all the way down to 0 voltage. So even the down-programmer running to GND might not be enough,  below a few 10 mV.
So I really see no good solution to avoid a bias current in the outputstage - though this could be small and in addition to the down-Programmer.

I did some simulations with a simplified output stage (more like a classic audio amp. ). Like in the original version bias changes the speed, but at least for this version the lokal loop (no feedback through OPs) is stable over a wide range of currents (e.g. 1 mA .. >1 A), just with different speed. So It might work to run on a rather low bias. However I stilll have some kind of large signal instability - it can oscillate in a nonlinear mode, triggered by a large current step. The original circuit is likely even worse in this respect, as there are currents compensating and possibly reaching 0.

The transistor part and a small output capacitor (e.g. 100 nF + 100nF/1Ohm) take care of the higher frequency part. Except that it is not compensating for the shunts, it allready is quite a powerful regulation. Below about 50-100 kHz it's limited by the shunts, the higher frequency part depends on the current, and can be below 1 Ohm even at higher frequencies.

So the OPs only need to fix the lower frequency part, e.g. below about 5-50 kHz. Here no fancy extra timing adjustments are needed,  just the one integrating capacitor can be enough. Having a little "gap" between the output stage and the OP part is actually positive as this ensures damping. So finding the right tunig of the system can be rather straigt forward: Adjust R23/C9 as to make the transistor part stable, even at low load and as little output caps (especially the one with damping) as possible. R23 ist likely not that critical so a value from simulation should work. The cap. in the OP part is rather simple: reduce until it oscillates, and than increase be a factor of something like 2 to 4.

Using the OP all the way to higher frequencies gets tricky,  as the output stage is current dependent in this range. Thus a low bias would require a rather slow regulation. Also tunig in real word could get tricky, as this is all one system, no simple separation in 2 subsystems.

[prasimix]

Hi Kleinstein and thanks again for spending time analyzing the circuit. Is it possible for you to post here some simulation results that shows impact of i.e. C15? I'm not able to replicate your findings (nor I'm so skilled to follow all your suggestions). Also I'll appreciate if you can post schematic/spice model with modifications that you think can improve performance of the existing solution. I'm ready to order a new PCB prototypes but I can wait a bit and make another revision if this make PSU even better.

[Kleinstein]

I did not get lucky with the output stage from above. There are 4 weak spots:
1) Turning the mosfet on is faster than turning it off. The other way around is more helpful.
2) It needs quite some negative supply - a PNP would save something like 2-3 volts
3) the down pragrammer is only loosely coupled, and needs quite some bias currents - still no adjustment for the output bias.
4) the MOSFET stage is rather slow at low currents - so some current is needed to keep a reasonable speed

So a did simulations with a slightly modified output stage, without the option to turn of the down programmer. It still is somewhat similar, but not that much. I still need a little more time. Currently only a simplyfied (no sense inptuts) voltage regulation is working. Still there is some nasty large signal oscillation after large steps.

[prasimix]

As I understand with DP that is always active in parallel with Out enable (what is a case with the original Liv's circuit) and -9V that I bring from pre-regulator that mentioned weak points are solved in good enough manner. Or we shouldn't be satisfied with good enough and try to improve it further?

Looking forward to see your model and simulations when you find a time to play a little with them. 

[Kleinstein]

Looking at the small signal (e.g. AC analysis)  the circuit kind of works - though not very fast, good.

The big problem is still have, is that there is this kind of large signal oscillation, when the output reaches saturation. This could turn out to be a real show stopper, though it mainly apears at large capacitive load (e.g. 1000 µF low ESR) and still rather moderate voltage amplitude. To me it looks more and more like a principle problem when having two nested loops, but no special anti-windup provisions.

Having two DP parts in paralle active is not a problem, the output stages should still have there amount of bias. Of cause there still should be the option to turn of the output entirely. However the current circuit still has the divider as a kind of minimum load, allways connected - so even if the DP is turned off there will still be some slow discharging. The rather high impedance of that devider is one point that makes the output stage difficult.