0.65mm BGA rules suggestions

[ali_asadzadeh]

Hi,
I have designed a 4 layer board for i.MXRT from NXP, unfortunately they are 0.65mm BGA, I have uploaded the Gerbers to jlcpcb, and they say with chinglish response that they can not produce them

So, I'm out of Ideas on what size of Via and trace and clearances should I choose, to be able to manufacture the boards cheaply!

I have contacted several times with them, they would not suggest anything for the design rules ,

Their response is

the minimum bga should be 0.45mm at least with a holes of 0.2mm, and 0.1 mm for the the trace thickness and space is ok, but the space from the bga has to be 0.127mm at least.

So the question is how should I change the design?

[OwO]

Distance between pad and trace need to be a bit bigger than the usual clearance specs because soldermask definition isn't perfect and mask opening should be a bit bigger than the pad. I think what they mean is you have pad to trace spacing that are < 0.127mm, and there is a high risk of bridging. Maybe post your layout so we can see what else may be wrong.

The smallest supported via is 0.2mm drill with 0.45mm outer diameter. JLC also has a strange requirement of 0.127mm clearance between via outer ring and trace, while the usual trace to trace clearance is 0.1mm.

[ali_asadzadeh]

I have chnaged the vias to 0.2mm hole and 0.45mm Diameter, I think it can not be done there!

This is some part of Top layer. Any Ideas? have you done 0.65mm BGA at jlcpcb?

[cgroen]

Ali,
I have now done 3 different designs with NXP 0.65 BGA (i.MXRT 106x) using JLCPCB without any problems at all!
I too started by asking them for specs (and the violation of them), I was told basically the same as you were "we can't do it".
Anyway, that did not stop me
I use 0.2mm holes and 0.356 outside VIA diameter, and there has been no issues at all

[cgroen]

This one was a test of HyperRAM, also using 0.2/0.356mm VIA, all was perfect
(stencil and a hotplate)

[stmdude]

I've done 0.8mm BGA reliably at JLC.

0.45/0.2mm vias, 3.5mil trace/spacing.  They support will say the trace/spacing needs to be 0.1mm (even touch their capabilities page says 3.5/3.5mil), but you can ask them to produce "at risk".

Seems like you can shrink the vias (but not the drill-size) a bit, and I wouldn't go below 3.5 mil either (I've had issues with thinner traces than 3.5mil at JLC).

I'm currently doing a 0.65mm BGA with the same rules (NXP iMX8M), and it seems to fit.

[ali_asadzadeh]

Ali,
I have now done 3 different designs with NXP 0.65 BGA (i.MXRT 106x) using JLCPCB without any problems at all!
I too started by asking them for specs (and the violation of them), I was told basically the same as you were "we can't do it".
Anyway, that did not stop me
I use 0.2mm holes and 0.356 outside VIA diameter, and there has been no issues at all

Thanks, my first design was 0.2mm via hole and 0.35mm diameter! they told they can not do it, and I should change it? how did they done it for you? do you have your order ID so I can ask them that you have done it for my friend with similar specs?

[cgroen]

Ali,
I have now done 3 different designs with NXP 0.65 BGA (i.MXRT 106x) using JLCPCB without any problems at all!
I too started by asking them for specs (and the violation of them), I was told basically the same as you were "we can't do it".
Anyway, that did not stop me
I use 0.2mm holes and 0.356 outside VIA diameter, and there has been no issues at all

Thanks, my first design was 0.2mm via hole and 0.35mm diameter! they told they can not do it, and I should change it? how did they done it for you? do you have your order ID so I can ask them that you have done it for my friend with similar specs?

Well, I have not done anything special at all. I just did the design and uploaded it to JLCPCB (I'm at 65 different designs with JLC now, all have been flawless) There were no comments back of any sort. I used 0.127 mm tracks (5 mil)
Maybe try and mimic my settings, 0.22mm and 0.356mm (14 mil outside) and see if that passes ?

[ali_asadzadeh]

Thanks, my track and clearance is 0.1mm or 3.97mil, also my BGA ball size is 0.3mm

If your track size is 5mil, what's your clearance? Altium would complain about the Via and track clearance if I wanted to route it out straight

[cgroen]

I use 3.5/3.5 mil width clearance, and 5 mil track/via clearance
The VIA's below are 0.2/0.356mm
You need to be clever/careful with what can be routed this way

[ali_asadzadeh]

Thanks for sharing, So I have changed the rules to these, Are they correct?

[ali_asadzadeh]

Also when I'm setting these rules set, Altium would generate a DRC and does not let me route the internal tracks, is it possible for you to share at least some parts of your PCB?

[ali_asadzadeh]

After changing the track and clearance sizes to 3.5mm and changing the via to track clearance to 5mils, and changing the via's to 0.2mm hole and 0.356mm diameter, they still say's that they can not produce them.

Here is their answer!!!

After the hole of 0.2mm in the original document is increased to 0.3mm, the hole-to-line is only 0.125 mm. You need to modify the document: the hole-to-line spacing can be increased to more than 0.2, please see the position indicated by the arrow in the picture.

Hello, is this document the same as the previous one, or can it not be produced?

[cgroen]

This is very strange, as I said, I have 3 different designs using exactly that 
I will have another one going (with same specs) in a couple of days....wonder how that will go

[amyk]

It looks like a precision issue. You're just a little over 2um outside of the spec.

[ali_asadzadeh]

It looks like a precision issue. You're just a little over 2um outside of the spec.

I do not get it? what do you mean?

This is very strange, as I said, I have 3 different designs using exactly that 
I will have another one going (with same specs) in a couple of days....wonder how that will go

Do you have an order ID, so I can refer to them?

[cgroen]

Ali,
I checked your design, it seems you break the 5 mil spacing between via and tracks multiple places?
When I run the DRC checker that I have adjusted for JLCPCB rules, I get 1533 errors and 4 warnings...
673 is clearance warnings, 173 silk to solder mask clearance and 55 board clearance errors (and some minor ones)
My bet is that there are so much wrong that they flag the board even though you use the same hole and via sizes as I do.
I have just submitted a new design with the same sizes in again (this is the 4th design I'm doing now with the i.MXRT106x using these VIA's) it was reviewed by JLC, approved, I payed for it, and the are now in production.
Sorry, I'm not going to supply order numbers or such.
Hope you find a solution (or another PCB producer, maybe that is easier just to do that, find some that can handle the higher requirements)

[ali_asadzadeh]

Hi cgroen, thanks for the update, would you please take some pictures of your design rules at least? in my Altium this number of errors that you say would not generate by hitting DRC, maybe I have set some rules in a wrong way!

Also I have paid them and then they said they can not produce them

[bson]

Isn't the smallest hole they specify 0.3mm?  So if you give them gerbers with a 0.2mm hole they're going to use a 0.3mm drill bit, and there will be almost nothing left of your annular given the 0.350mm via diameter?  Isn't this what they're telling you?

Edit: Oh wait - I checked, and their spec for 4/6 layer is 0.2mm holes.  So I fail to see the problem with e.g. 0.2/0.4 vias.

Edit 2: I checked some of the boards I've had them make, and have used 0.2/0.45 in tight spots.  No complaints from them or problems with the boards.  0.45 might be a little big for a 0.65 BGA though.  (I've only done 0.8 and 1.0 BGAs.)

[aandrew]

Be careful with those thick traces off the BGA pads; I ran into some nasty reflow issues with an 0.8mm BGA (STM32F756) doing the same thing. My thinking was to make wide traces to the vias, but apparently that is tricky to profile. Out of ten prototypes, 5 had to be reworked.

Interestingly enough, the 1.0mm pitch BGA (10M16 FPGA) beside the 0.8mm one seemed to be just fine.

[ali_asadzadeh]

Be careful with those thick traces off the BGA pads; I ran into some nasty reflow issues with an 0.8mm BGA (STM32F756) doing the same thing. My thinking was to make wide traces to the vias, but apparently that is tricky to profile. Out of ten prototypes, 5 had to be reworked.

Interestingly enough, the 1.0mm pitch BGA (10M16 FPGA) beside the 0.8mm one seemed to be just fi

Thanks for the tip

[dmitriy_1_b]

Hello. I have the same problem I found that post in internet. At the same time I write to jlcpcb. And they answer:
"Hello there,

Thank you for your attention and pointing out this.

Actually Min. BGA Pad Dimensions should be 0.25mm for mutiple layer and we will correct it soon.

Meantime, there should be no problem for the the design in your image."

PS. Now I also understand that with this rules I can place via in the middle of the bga pads.

Maybe to someone like me, that google that thing,  that was helpful.

[ali_asadzadeh]

If you manage to neckout every pin and JLCPCB accept it, please share the results