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Electronics => Projects, Designs, and Technical Stuff => Topic started by: super7800 on November 06, 2024, 09:26:15 pm
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I am designing a lock-in amplifier circuit. I have never used or designed one before.
The sensor (in simplest terms, a bridge) is excited with a bipolar 10mA signal. A voltage is then read off. The sensitivity range is from 50mV/Full-scale to 110mV/Full-scale, however the linear range of the sensor is huge, to where the signal is often < 0.05mV. The sensor resistance is ~2R.
Signal Chain:
Instrumentation Amplifier (20x) -> cascaded PGA gain stage (1x to 512x) -> wideband tap-off -> AD630 in a lock-in amplifier configuration -> 4th-order Butterworth filter (400 Hz) -> Narrowband/DC tap-off
The ADC then has an analog switch to select between the narrowband/dc and wideband modes of operation. The ADC is 24-bit 512 kSPS (ADS127), with signal analysis being done with an FPGA. Goal is 4-1/2 to 5 digits.
In wideband mode, noise floor is not a strong design criteria. The normal mode of operation is narrowband and DC measurements, which is where the noise floor matters.
I have never designed a lock-in amp before. I also rarely work with demodulators. Specific questions:
1) Is the signal chain ideal?
2) Should I implement a band-pass filter before the AD630?
3) Is doing the "heavy lifting" in the digital domain the best choice?
Schematic attached. It is annotated. It is preliminary.
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To optimize the input amplifier's noise contribution, you need to specify the resistance of the bridge.
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Not a lock in amplifier expert, but your PGA seems a bit too complicated. Having both multi-stage taps and switched gain stages seems like overkill. I would also be concerned about the PGA saturating on noise signals at higher gains. For reliable operation, it could be helpful to add some clipping detection to the signal chain - otherwise your PGA could be saturating on a noise signal which isn’t visible after the AD630.
In terms of filtering, I would expect to see a band pass filter straight after the instrumentation amp U79. The system noise is likely to be dominated by U79 (and its gain setting resistor), so it seems - in my inexpert and possibly wrong opinion - unlikely to worsen overall noise. My motivation to move the band pass filter closer to the input is to get rid of DC offsets and noise as soon as possible.
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With a good resolution ADC there is no more need for a fine adjustment of the analog gain. It should be OK to have just 20 dB ( x10 voltage gain) steps.
This could simplify the amplifier part. To make full use of the low noise INA at the very input the input amplifier should run with more gain ( x 20 is a bit on the low side, though not very bad). The first amplifier stages should be low noise, that later stages are far less relevant.
For the LT1128 already 10 K are on the high side - it's a rather speciallized part for low resistance signals (e.g. < 500 ohm). A more universal amplifier would be the OP27 or newer similar type. For the part after the demodulator the DC precision is relevant and speed much less.
it came up before, AFAIR the AD630 is not such a great solution for an accurate lockin as it has limitations with the linearity and offset drift. A solution with CMOS switched may be better.
In most cases one wants quite some headroom also at the demodulator output and thus part of the gain (e.g. x 10 or x 100) also after the demodulation. Especially for the highest overall gain, some gain should be after the demodulator.
Usually the filter after the demodulator is more like 1 st or 2nd order and often quite a bit lower than 400 Hz. One may want a variable timing here. With a relatively fast ADC to read the signal much of the low pass filtering could be done in the digital domain anyway.
With a not so fast (some 5.4 kHz is indicated in the plan) signal one could even drop the whole analog demodulator and do the whole demodulation in the digital domain instead.
A bit more information on the applications (frequency range, type of signal / background) may help.
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For low noise operation the first stage is the most critical, you wan't the lowest noise device, noise consists of resistor noise, voltage noise of the input amp and of course input current noise multiplied by the input resistance. If the input resistance is relatively high then you wan't low input noise current e.g. JFET input stage amplifier, if voltage noise is dominant then a bipolar input stage amplifier. The first stage should have the most gain possible(without saturation) so that the following stages effectively have little contribution to the noise budget.
A lockin amplifier will also have glitch or switching noise, which can often dominate the low level noise performance, so if you have a low level signal some AC amplification can be of benefit, hence your PGA could be quite useful.
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The idea is the three modes of operation, Wideband, narrowband, and DC. Narrowband(400Hz) and DC are after the lock-in and filtering. For wideband, it taps off pre modulator, and the sensor would receive a constant current. Typical use-case, the signals we want to see is < 20 Hz, but in wideband may be > 50KHz.
The excitation will be approximately a 5.4KHz square wave.
I considered full digital. Its a trade-off. I plan to use a low-cost low-additional-parts FPGA, but there isn't a strong reason I couldn't use a better one, its a trade-off between analog complexity and cost vs digital. I do not have enough experience with either method to make the call, and I am very open to advice.
Sensor resistance is 2 ohms.
@Kleinstein if you have any links comparing the two methods, let me know. I looked into doing it both ways, but i could not find a strong evidence either way. some say the AD630 is better, while others have the opinion that a CMOS switched method is better. So i should move one of the gain stages after the demodulation?
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At 2\$\Omega\$ source impedance, a bipolar-input op amp is preferred for noise performance.
Most commercial analog lock-in amplifiers use a JFET input, for a more general range of source impedance.
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One should definitely have at least some of the gain after the filter. This could be as little as not having a divider from the +-10 V OP-amps at the filter to the +-2.5 V range of the ADC. For the dynamic range this acts like a gain of 4. This is still relatively little - suitable for a rahter clean signal.
If the there is significant background (e.g. mains hum) one may want extra gain to have headroom at the modulator and still use much of the ADC range. The ADC has quite some dynamic range and can this way compensate a bit, by not using the full ADC range. The ADC is still a limited by DC drift - likely more than the normal noise (at least for a low BW).
From just the offset specs (especiall the implied drift) the AD630 does not look that great. As a differential BJT based amplifier chances are that the offset drift also gets better when the the offset is trimmed. With the offset trim at the AD630 it may be an OK choice when it comes to drift. While the offset itself should not be a problem, the trim usually also reduces the offset drift, and this can be a relevant parameter for the demodulator if one wants relatively high resolution.
With a 2 ohm source and 5 kHz frequency one could even consider a transfromer at the input for even lower noise.
The describtion sounds a lot like some DMS or similar application. So not so much a general lockin, but more a sprecial case with relatively fast modulation. This would allow for suppressing the mains hum with a high pass. The wide band mode may still want also the lower frequencies, possibly all the way to DC.
Generating the modulation signal is the easier case, as one does not need a PLL or similar for the reference channel and can run in sync with the ADC clock.
Digital filtering (low pass filtering the signal after the modulator) can be relatively simple - to a large part the right filter would be a SINC1 type, so simple averaging over a certain time window. With the right length (full number of periods of the modulation) one can get very good suppression of the carrier frequency and still a good bandwidth. The finite settling time can be an advantage for a digital filter. Even the 400 Hz BW limit could be done largely from digital filtering, so that a simpler analog filter should be sufficient. I have used the combination of relatively little analog filtering and digital averaging with a lock-in amplifier and this worked really well - especially for long averaging, where the settling time can be relevant.
Similar digital demodulation is no magic: just run everything in sync and add / subtract with maybe a few samples of dead time around switching. If using the simple square wave demodulation like the AD630 does (and possibly a dead time in addition) it is not much more effort than the low pass filter alone. One could still keep that option (allow for a synchoronous clock and some sync signal to/from the ADC) and use the "wideband" path for this.
As an advantage the DC drift of the ADC would also be suppressed and thus more usable resolution from the ADC. This would especially an advantage of there is little dynamic reserve needed (corresponds to little gain after the filter), with a relatively clean signal.
For me the question would be if an FPGA or µC or maybe both together would be more suitable. It somewhat depends on where the result goes. It is not that fast, that a modern µC could not do it without FPGA support.
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Is this '5.4KHz FPGA' source is phase variable?
I added annotation \$\Phi 1\$, \$\Phi 2\$.
[attachimg=1 width=480]
I ask this because you say
2) Should I implement a band-pass filter before the AD630?
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For the filtering question "2) Should I implement a band-pass filter before the AD630?", it depends on the signal (how much interference) and what one intends to look at.
For looking only as the base frequency (e.g. some 5 kHz) one would need the filter. If the experiment is largely wide band, like a DMS bridge, RTD demperature sensor or hall effect it is usually better to not have a filter an use the full square wave (optionally with some dead zone). A filter to suppress mains hum could help, if there is a lot of it.
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For me the question would be if an FPGA or µC or maybe both together would be more suitable. It somewhat depends on where the result goes. It is not that fast, that a modern µC could not do it without FPGA support.
to give a high-level system overview, this is board 1 of 2. The mainboard has a samd51 micro communicating with a pc. it is quite busy. Not shown on the schematic, but the inputs to the circuit can be connected to the self test of the main board - 16-bit DAC +-10V. Perhaps with the use of Digi pots some offset nulling of the AD630 can be had. The micro or FPGA on this board (the lock in amplifier) only handles the data manipulation and sets the gain. it is a slave to the main processor.
So, what I'm hearing is:
-2nd order lowpass, further filtering in digital domain
-Less fine-adjustment gain setting on input, add gain to output
-I should explore the option of alternatives to the AD630. (CMOS switched, etc.)
The AD630 doesn't list an adjustment range, or at least I cannot find one. If its not stable, it may not even be worth adjusting.
The sensor element is hall effect. The current source is isolated GND from the measurement path.
A question: which would have better theoretical performance in this application, an AD630-based lock in amplifier, or a full digital lock in amplifier implementation? (i.e. Instrumentation -> PGA -> Antialiasing Filter -> ADC)
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If the AD630 for analog demodulation or digital modulation is better depends on the quality of the ADC and amount of interference signal in the signal. The AD630 can suppress some of the interference from frequencies well outside the frequenies of interest. This reduces the demand on headroom of the ADC.
Direct sampling the signal needs some additional headroom for out of band signals and noise, but avoids the errors (offset drift, linearity) of the AD630 stage.
With adjustment of the offset the offset drift should also get rather small. This is at least the normal case with BJT based amplifiers.
The nasty part may be more the switching spikes that may change with temperature and this way cause drift for the output signal.
Modern digital LI amplifiers outperform the old style analog LI amplifiers in most aspects.
Another plus for the digital solution could be that one can add a short dead time phase then the sensor current switches. This could avoid errors from that switching part.
So I would expect the digital solution to be supperior if the ADC is reasonable good. The suggested ADS127 looks good enough.
Chances are that both ways could reach the point that simply the noise is limiting.
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I should like to suggest using a pair of moderate width filters that can have the center frequencies shifted if you expect to need narrow filters. This avoids the Fourier wide - narrow problem.
Have Fun!
Reg
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Shown below is an example of a lock-in bridge amplifier from Linear Technology application note 43. This gives some idea of what is required and how simple it can be.
The transformer is used for common mode suppression, so an instrumentation amplifier is not required. However there are other ways to implement common mode suppression using the bridge excitation, like the other example shown below from the same application note.
The bandwidth filter is at the output and just a single pole. In a digital application, I would synchronize the digitizer to the AC excitation so it would then reject the chopping frequency.
My personal experience is that square wave excitation can have problems with dielectric absorption (like printed circuit board hook?) in the bridge wiring, so there may be some advantage to using AC sine wave excitation.
2) Should I implement a band-pass filter before the AD630?
I would be very careful about bandpass filtering because the demodulation is phase sensitive, which will limit how narrow the bandpass filter can be without introducing phase error over time and temperature.
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I believe that sine-wave excitation with square-wave switching in the synchronous demodulator is normal for lock-in amplifiers.
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I would be very careful about bandpass filtering because the demodulation is phase sensitive, which will limit how narrow the bandpass filter can be without introducing phase error over time and temperature.
Yes. Thats why ask about phase. Bandpass filter will be troublesome if one can't adjust phase.
100nF,10K \$\Omega\$ Highpass filter(AC coupling) introduces a 1.68 degree phase shift at 5.4kHz. about 5 degree for 3 stages - not big deal, but it is phase sensitive so it should be taken into account.
A question: which would have better theoretical performance in this application, an AD630-based lock in amplifier, or a full digital lock in amplifier implementation? (i.e. Instrumentation -> PGA -> Antialiasing Filter -> ADC)
If you compareing analog single-phase LIA and digital dual-phase LIA, it's almost no contest. Dual-phase is better. There is no point making single-phase digital LIA. It's possible but ... doesn't make sense to me.
Does such a thing exist?
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I believe that sine-wave excitation with square-wave switching in the synchronous demodulator is normal for lock-in amplifiers.
The excitation is normally not directly part of a lockin amplifier. It depends on the experiment.
Square wave demodulation is very common for analog LI amplifiers, as a sine demodulation is difficult to build and prone to drift.
To suppress the sensitivity to the harmonics an analog bandpass can be used, but it can add phase errors.
For application with a more square wave modulation a demodulation with a square wave is usually also better, at least noise wise.
Noise wise the demodulation should ideally follow the excitation.
If a dual phase demodulation brings an advantage depends. Especially with low and stable phase shifts at low freuqency there may not be much (if any) advantage of a 2nd phase. The example here is such a case.
For this application a single phase digital demodulation would make absolute sense. I would also add a little dead time for the switching part to reduce possibel delay effects, that may not be very stable. So look at the signal more in the time domain, not just the frequency domain as usual for LI amplifiers. The small phase shift from AC coupling should not be such an issue as it should be rather stable.
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I am designing a lock-in amplifier circuit.
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Goal is 4-1/2 to 5 digits.
I have only limited experience with lock-in amplifiers, but I understood them more as being used as null-detector. Used in physics lab to distinguish between signal and no signal. The analog MCM was sufficient as indicator for that. The demodulation math looks a bit hairy, getting linearity to better that 100ppm might be a challenge (iiuc, even 0.1% would be considered quite good).
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Analog demodulation, especially a sine multiplication is indeed tricky and limited linearity / gain stability. That part is more good for a zero detector.
With switched demodulation the accuracy can be good and linearity may not be such an issue. There could still be frequency dependent effects - so the gain accuracy over frequency may not be that high, but it could still be very linear and long time stable. With digital demodulation the linearity and stability is essentilly what the ADC and amplifier provide, and this can be really good with modern ADCs. Chances are the gain stages with there frequency dependence would limit the accuracy. Things are a bit easier than modern DMMs with digital RMS, as the noise background averages out and the BW is limited.
Usually the higher precision DMS are read with modulation and demodulation, similar to what is planed here. These are more limited by the DMS, not the amplifier part. If wanted the amplifier / demodulator should work to the sub ppm range.
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I believe that sine-wave excitation with square-wave switching in the synchronous demodulator is normal for lock-in amplifiers.
I have always used square-wave excitation for the reason Kleinstein identifies despite the dielectric absorption problem; it is easier to control the amplitude with square waves than sine waves. But this AC error makes precision better than a DC excitation design with modern low drift DC amplifiers difficult. Of course a lock-in amplifier has other advantages like noise rejection.
I would be very careful about bandpass filtering because the demodulation is phase sensitive, which will limit how narrow the bandpass filter can be without introducing phase error over time and temperature.
Yes. Thats why ask about phase. Bandpass filter will be troublesome if one can't adjust phase.
100nF,10K \$\Omega\$ Highpass filter(AC coupling) introduces a 1.68 degree phase shift at 5.4kHz. about 5 degree for 3 stages - not big deal, but it is phase sensitive so it should be taken into account.
If it was just a matter of adjusting the phase, then it would not be a problem. The problem is that a narrow bandpass filter has a large shift in phase around its passband frequency, which makes phase sensitive to anything which affects the filter or frequency.
10 MHz calibration sources and distribution amplifiers have the same problem if phase is to be maintained. The solution sometimes used is to notch the lower harmonics, and then implement a low-pass filter further away from the frequency of interest.
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so, taking this discussion into account, it seems that a pure digital solution would be the better performance option, or at least the most likely to work without revision.
Square wave excitation current is planned to be used.
I have updated the signal chain accordingly.
Input MUX -> INST AMP -> PGA -> ADC Driver (antialiasing) -> ADC -> FPGA -> MICRO (on mainboard) -> PC
I was going to go with an ICE40 For the FPGA, but i might need more grunt, e.g. LFE5U.
The ADS127, AD7768 seem viable options for the ADC.
A revised schematic is attached.
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There is still the issue with the relative low gain for the input amplifier - it does not make full noise of the INA potential. The gain resistor has way more noise than the amplifier. The other channels may still need the lower gain. So one may have to accept a few compromises.
The PGD stages are not very accurate, with the switch resistance in the gain path. There are better ways to switch the gain. Normally one should not even need such fine gain step: the ADC should have plenty of dynamic range, at least with not too high a bandwidth.
At least only 1 stage with fine gain should be sufficient. The LT1028 is also not a good choice for the high impedance circuit - the current noise would make it rather noisy. I don't think one could use that much gain: the input noise of the high grade ADCs is not that bad.
The AC coupling has a 1 ms time constant and is thus already adding some phase shift and limiting the lower frequency limit. One may not need so many AC coupling capacitors. If mains hum is an issue, a notch filter would be more practical solution.
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There is still the issue with the relative low gain for the input amplifier - it does not make full noise of the INA potential. The gain resistor has way more noise than the amplifier. The other channels may still need the lower gain. So one may have to accept a few compromises.
The reason it is so low is that the full-scale of the sensor can be +-110mV, but signal levels can be as low as <50uV.
The PGD stages are not very accurate, with the switch resistance in the gain path. There are better ways to switch the gain. Normally one should not even need such fine gain step: the ADC should have plenty of dynamic range, at least with not too high a bandwidth.
At least only 1 stage with fine gain should be sufficient. The LT1028 is also not a good choice for the high impedance circuit - the current noise would make it rather noisy. I don't think one could use that much gain: the input noise of the high grade ADCs is not that bad.
Frontend such as this (attached)?
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The idea is the three modes of operation, Wideband, narrowband, and DC. Narrowband(400Hz) and DC are after the lock-in and filtering. For wideband, it taps off pre modulator, and the sensor would receive a constant current. Typical use-case, the signals we want to see is < 20 Hz, but in wideband may be > 50KHz.
The excitation will be approximately a 5.4KHz square wave.
Do you generate the 5.4kHz from your system ?
If you do, you can use a simple synch detector, (eg as in #13) which can dig into the noise of 5.4kHz and give you the 20Hz BW out for the ADC.
That eases the digital side.
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The updated front end is a bit to the other extreme. There is likely no need for super accurate gain, as there is the less accurate input stage in front. So there are simpler resistor pairs (just 0.1% resistors, Susumu RM... or ACAS series) available than the LT5400. I don't think one would need the last gain stage, as the noise for the ADC input should be well less then 2000 times the input stage noise.
The MUX at the input would add some extra noise from the resistance (some 125 ohm each). One should consider a lower resistance MUX.
P.s.: a small additional point: the path to U88 S4 may want a resistor in series. This would especially be the case if U88 is powered from +-2.5 V as most of the signals should be low voltage.
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I don't think one would need the last gain stage, as the noise for the ADC input should be well less then 2000 times the input stage noise.
you are correct in that I don't need the third gain stage (4 gain steps). Better to have three gain steps.
If mains hum is an issue, a notch filter would be more practical solution
I would think it would be better to filter this out in the digital domain, correct?
The MUX at the input would add some extra noise from the resistance (some 125 ohm each). One should consider a lower resistance MUX.
Good point. I will switch all the analog switches to relays. SIP-1A05.
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Reed relais are low resistance, but they also tend to produce thermal EMF and the power consumption can be an issue.
There are lower resistance switches if needed (e.g. ADG1409). The later mux to choose between the amplifier stages would not be critical with the noise / resistance.
For the lowest gain path one could consider a divider (e.g. 1:4 or so) after the INA that is still powered with +-12 V to than get a path to the +-2.5 V powered part. This would allow to have more gain at the front and less noise from the gain setting resistor / INA.
If the mains hum level is low, the ADC can handle this. This problem could be a relatively high level of mains hum, that could drive an amplifier to saturation if the gain is high. A notch filter is also not ideal, but could be an option if there is really a lot of background. If there is only a relatively small hum level, there is no need for a notch and digital filtering should work better.
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For the lowest gain path one could consider a divider (e.g. 1:4 or so) after the INA that is still powered with +-12 V to than get a path to the +-2.5 V powered part. This would allow to have more gain at the front and less noise from the gain setting resistor / INA.
Attached. Also a preliminary layout.
If the mains hum level is low, the ADC can handle this. This problem could be a relatively high level of mains hum, that could drive an amplifier to saturation if the gain is high. A notch filter is also not ideal, but could be an option if there is really a lot of background. If there is only a relatively small hum level, there is no need for a notch and digital filtering should work better.
I expect the mains hum to be low, so i will proceed with the idea of digital filtering.
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I see no need for the extra buffer amplifier U21.1. There is a buffer already after the mux.
I would consider having the path via the divider DC coupled ( other side of C39). With so little gain this should work and could help detecting problems without an external measurement. It would also reduce the required coupling capacitor.
With 1K/10 K at the -10 amplifier stage the coupling capacitor should likely be larger anyway or one should use larger resistance.
A coupling capacitor in the 1 µF range would likely be PE film and not longer C0G.
The path to S2 at the mux should have a series resistor to limit to current incase the voltage goes beyound +-2.5 V.