EEVblog Electronics Community Forum
Electronics => Projects, Designs, and Technical Stuff => Topic started by: ZeTeX on December 24, 2015, 11:12:12 pm
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hi,
my psu started to osciliate at 0.01R load and current and voltage set to max (25V 1A).
I tried fixing the osciliation but I could not get it to stop.
what might be the problem?
here is the osciliation, the green waveform is the current at R19 (load) and blue waveform is the output of the error amplifier U2.
(https://i.gyazo.com/4cbb24835f5804f2a95284aad6cd7491.png)
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Try some resistance in series with C2, C3?
Tim
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Try some resistance in series with C2, C3?
Tim
tried alerady only with C3 as C2 doesnt do anything while in constant current. didnt work :(
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How can it be clamped to zero for a msec without the output current dropping like a brick? Is OUT winning over the control loop?
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U2 with no fb resistor? only a 560p dominant pole ? expensive operational amplifiers used as comparators... will work (and will oscillate as a result of obvious common sense) . op-amps used as a comparators are almost always sourced from textbooks theory, and recognised as gospel to some. use comparators LM393 its cheap.
try probing all the high gain nodes. take all stuff that haven't been considered as calculated parameters and start over again. like what is the reasoning behind L1 at the base of the power BJT. looks like random components being thrown around.
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The current regulation will need a capacitor paralel to the load - does not need to be large (e.g. 1 µF should be enough), but it must not bypass the shunt.
The extra amplifier for the current signal is also a problem: even with a fast OP it adds some delay.
The whole design is strange - why would one use a floating regulator and a low side shunt - that does not work well together: either have the OPs supply relative to the negative side and a low side shunt, or have the floating supply an the shunt directly at the emitter.
When well designed, the OPs (or at least one at a time) will work in linear mode even withoout DC feed back directly at the OP. The 560 pF integrating capacitor is not even that small. The capacitor in the current loop looks rather small though.
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The current regulation will need a capacitor paralel to the load - does not need to be large (e.g. 1 µF should be enough), but it must not bypass the shunt.
The extra amplifier for the current signal is also a problem: even with a fast OP it adds some delay.
The whole design is strange - why would one use a floating regulator and a low side shunt - that does not work well together: either have the OPs supply relative to the negative side and a low side shunt, or have the floating supply an the shunt directly at the emitter.
When well designed, the OPs (or at least one at a time) will work in linear mode even withoout DC feed back directly at the OP. The 560 pF integrating capacitor is not even that small. The capacitor in the current loop looks rather small though.
a 1uF cap in paralel to the load didnt work unfourmently
the op supplys are now ground refrenced and not floating.
I found out that any set current above 750mA make it osciliate, still no clue.
EDIT: by placing a 470u cap at U2 output it seems to work, thats why I know I need to slow down the op amp at least, still playing with the value to see if I can fix this.
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EDIT: by placing a 470u cap at U2 output it seems to work, thats why I know I need to slow down the op amp at least, still playing with the value to see if I can fix this.
Since you are using a PWM pre-regulator and floating voltages around it, you might want to check possible correlation between preregulator output variation and your output oscillations.
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It is turned down awfully slowly (0.1uF?). And having a transistor in the loop implies gain, though it is turned down awfully low too (10k emitter and collector), so much that it raises the question, what is it doing there in the first place?
Tim
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The transistor in the loop is just a darlingtion only drawn in an unusual way.
Inceasing C3 might be necessary - I would start with more like 1-10 nF and see how much smaller is possible.
The voltage loop is also quite fast with R4 at only 1 K.
It's also a good idea to have a resistor from base to emitter at the output transitor (e.g. 100 Ohms range).
C7 should more go to the upper side of the shunt, not GND directly. C1 should better no be there at all. In the final circuit I would prefer to have not one C7, but a combination of a low ESR cap (e.g. 1 µF) and one with significan ESR (e.g. 10 µF low ESR electrolytics).
The type of oscillation shown looks like it involved saturation of the OPs - so the regulators go into a kind of windup, when the other regulator is active. This typ of oscillation can be rather tricky, as it is beyond simple linear small signal theory. One counter measure for this is having a feedback of the voltage regulator from behind the diode too. So have something like 1 K and 1nF in series from the kathode of the two diodes to the inverting input of U1 and possibly reduce C2 a little.
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The transistor in the loop is just a darlingtion only drawn in an unusual way.
Inceasing C3 might be necessary - I would start with more like 1-10 nF and see how much smaller is possible.
The voltage loop is also quite fast with R4 at only 1 K.
It's also a good idea to have a resistor from base to emitter at the output transitor (e.g. 100 Ohms range).
C7 should more go to the upper side of the shunt, not GND directly. C1 should better no be there at all. In the final circuit I would prefer to have not one C7, but a combination of a low ESR cap (e.g. 1 µF) and one with significan ESR (e.g. 10 µF low ESR electrolytics).
The type of oscillation shown looks like it involved saturation of the OPs - so the regulators go into a kind of windup, when the other regulator is active. This typ of oscillation can be rather tricky, as it is beyond simple linear small signal theory. One counter measure for this is having a feedback of the voltage regulator from behind the diode too. So have something like 1 K and 1nF in series from the kathode of the two diodes to the inverting input of U1 and possibly reduce C2 a little.
I tried all what you said but it doesnt seems to have effect, I tried putting resistor from base to emitter but that makes the regulator limited to lower current.
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Is the preregulator involved in the oscillation ?
I would first do simulations without the preregulator - only if this is working Ok add it.
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Is the preregulator involved in the oscillation ?
I would first do simulations without the preregulator - only if this is working Ok add it.
suprise suprise, its the bloody pre regulator.
without the pre regulator it looks rock stable. 100000uF capacitor no osciliation, 1R no osciliation.
looks like <20us to enter current limiting so thats pertty fast.
here is the current schematic thats works, without all the modification you told me, I will have to try them, problem now that if its stable in ltspice how can I know it will be stable in real life..
(https://i.gyazo.com/8ecbf6c75149627ceea42f841ed1a20f.png)
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suprise suprise, its the bloody pre regulator.
Your pre-regulator could also work if Q5 is properly biased. Try pre-regulator without post-regulator and see what you'll got.