### Author Topic: Estimating time spent on Miller Plateau (maths)  (Read 1844 times)

0 Members and 1 Guest are viewing this topic.

#### Doctorandus_P

• Super Contributor
• Posts: 3569
• Country:
##### Re: Estimating time spent on Miller Plateau (maths)
« Reply #25 on: June 13, 2024, 07:40:20 pm »
Some notes:

The root cause of the Miller effect is that the gate-drain capacitance gets multiplied because of the voltage change over the drain node, and I do not really see that in formulas working with gate charges.

As soon as the miller plateau ends, the drain - source voltage is low. When the gate voltage gets higher, the drain - source channel resistance get lower. It can be reduced to about 1/3 with a gate voltage or 12V or so. I don't know whether that is significant in your application.

To simulate an uC output pin, a 5V "ideal" voltage source combined with a series resistor is a not very good approximation. From what I have seen, a resistor works quite well as approximation until there is around 2V over it. After that the uC just can't source more current and it starts acting as a constant current source. But of course this depends on the exact uC used, and even revisions (die shrinks) This is probably one of the bigger sources of error in your simulation.

Simulation is a good way to test a lot of things quickly, and get test theories, but it remains an additional tool. It is no substitute for real life testing. I still use breadboards quite a lot. Putting crystals (for an uC) on a breadboard is a *&^%\$#@! but plenty of uC's have breakout boards that fit in a breadboard. For High current connections, I used to use banana plugs just like anyone else, but I switched to using silicone insulated wires, stripped by around 15mm and then the strands soldered together just enough to keep them together, and combine that with Wago 222 (or the smaller rectangular 221 series) or similar. These can handle 30A, are quick to connect and disconnect, and you can re-use them around 200 times before the spring fatigues and the spring pressure gets noticeably low, and that is a good indicator for when to replace them.

#### T3sl4co1l

• Super Contributor
• Posts: 22012
• Country:
• Expert, Analog Electronics, PCB Layout, EMC
##### Re: Estimating time spent on Miller Plateau (maths)
« Reply #26 on: June 13, 2024, 09:28:31 pm »
The Miller multiplication is specifically about capacitance -- hence why the plateau is so flat, the incremental capacitance dV/dQ is very large.  The total charge however is irrelevant for Miller's theorem -- all that's needed is a linearizable range where the theorem applies.  In cutoff and saturation, gm --> 0 and those conditions no longer apply, thus starting and terminating the plateau.

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!

#### Lomax

• Frequent Contributor
• Posts: 582
• Country:
• Minimalist
##### Re: Estimating time spent on Miller Plateau (maths)
« Reply #27 on: June 13, 2024, 10:37:39 pm »
Thanks for the interesting discussion! I would like to understand the theory well enough that I can calculate the behaviour with some level of confidence, but despite spending many hours digesting some pretty dense (to me) application notes etc, and trying to replicate some of the calculations outlined in them, I don't seem to be making much progress. I still plan to use the BUK9880-55A MOSFET for the actual circuit but decided to work with the IRLL024Z to practice on the calculations, since I've got a working (if crude) SPICE model for it running in ngspice, which gives me the ability to double check my results.

I would like to be able to predict the switching losses with reasonable accuracy, and as a baseline I generated a full PWM cycle's worth of samples of the power in the MOSFET at 30 kHz, zeroed all the values outside the switch-on and switch-off regions and averaged the list of 30k+ samples. This gave me 0.034 W, which doesn't seem entirely unreasonable. Then I did the same at 10 kHz and got 0.013 W, which also seems reasonable. To test some different formulas against these baselines I made a spreadsheet with the known values from the datasheet, and the known values from the circuit, and used these values as inputs for three different switching loss formulas - all of which look incomplete to me since they do not take the gate resistance RG(tot) into account, which I know has a profound effect on the switching time and hence the switching losses. I would also expect all of them to rise by a similar amount when increasing the PWM frequency, but as you can see below they're all over the place. And yes, I have double checked the spreadsheet formulas. I'm tired and despondent but still determined to make sense of this  - can anyone help?

« Last Edit: June 14, 2024, 08:41:43 am by Lomax »

#### T3sl4co1l

• Super Contributor
• Posts: 22012
• Country:
• Expert, Analog Electronics, PCB Layout, EMC
##### Re: Estimating time spent on Miller Plateau (maths)
« Reply #28 on: June 14, 2024, 12:55:34 am »
Hm, something's missing in the top-right calculation 'cuz all three are proportional to Fsw and I don't know which one it was calculated with but if it's similar to "DMC" it should be around 5/15 or 6/18mW or whatever, but it's not changing at all.

I_G slipped a multiplier, it should be mA.  Also maybe worth noting it's average / DC supply, for clarity.

Incidentally, I don't have the part in question but here's a IRF510PbF with 1050Ω gate resistor and 15Ω drain resistor (somewhat inductive at this rate).  The capacitance kinda sorta seems two-segmented but it's definitely smoother inbetween than the SPICE model has it.

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!

The following users thanked this post: Lomax

#### Lomax

• Frequent Contributor
• Posts: 582
• Country:
• Minimalist
##### Re: Estimating time spent on Miller Plateau (maths)
« Reply #29 on: June 14, 2024, 08:17:03 am »
Hm, something's missing in the top-right calculation 'cuz all three are proportional to Fsw and I don't know which one it was calculated with but if it's similar to "DMC" it should be around 5/15 or 6/18mW or whatever, but it's not changing at all.

Well, it is changing, but not enough to show on the three digit (display) precision I'm using. Clearly not right though! I got the formula from page 3 here - though QGS2 is not known, so I'm using (QGS / 2) as a rough approximation, just to be able to test it.

I_G slipped a multiplier, it should be mA.  Also maybe worth noting it's average / DC supply, for clarity.

Ah, good catch! The units are only cosmetic unfortunately (if someone knows how to make LibreOffice Calc play nice with SI prefixes I would love to hear about it). Instead I multiply the values by the correct powers; you type "10" in the fpwm box and under the hood it's treated as 10*10^3.

Edit: Actually, hang on, IG should be in amps otherwise I have to transpose this as well when I use it. Things like G4*G3*(G8*10^3)*((((D8/2)+D9)*10^-9)/G13) gets old pretty quickly. I agree about the average; How about relabelling it IG(avg)? Seems a shady value anyway, since (again) it doesn't take RG(tot) into account?

Edit2: I think a possible way forward would be to calculate the rise and fall times rather than use the numbers from the datasheet, and use these times with the DMC formula. When changing rise time to 60 ns and fall time to 40 ns (which is what the simulation shows) the DMC formula gives me 0.036 W at 30 kHz and 0.012 W at 10 kHz which is extremely close to my baseline values. These times correspond to t2-t1 and t6 in this Vishay application note (p2-3).

« Last Edit: June 14, 2024, 09:02:37 am by Lomax »

#### Lomax

• Frequent Contributor
• Posts: 582
• Country:
• Minimalist
##### Re: Estimating time spent on Miller Plateau (maths)
« Reply #30 on: June 14, 2024, 09:43:20 am »
I'm trying to get tr ~60 ns here, but I get 129 or 27...

They do not say where they get VGS, so I can only assume this is my VG(drv). Their Ciss is also a little unclear because they never explain how Cgs and Cgd are calculated:

I have tried using both Ciss from the datasheet (380 pF) and the calculated effective capacitance CG(on) from (QGS + QGD) / Vgp = 1.83 nF. These are obviously wildly different values, but hey ho, I never get even close to the observed (in simulation) ~60 ns rise time.

Edit: I'm sorry, I had an error in my simulation: the measured rise time should be ~50 ns, not 60.

Edit2: I've managed to prove (to myself - I'm sure this is obvious to anyone who speaks math) that both of Vishay's methods for calculating tr produce exactly the same result when using the same value for the gate capacitance. The only problem is that using Ciss it's about half of what it should be, and using CG(on) it's two and half times too large:

Not sure if that qualifies as progress, but it's at least nice to know.

Edit3: Maybe I'm calculating the gate capacitance during t2 incorrectly; using (QGS + QGD) / Vgp gives the Miller Plateau (t3) capacitance, which is where the gate capacitance reaches its maximum - but I'm interested in what happens before that, at the threshold voltage. So perhaps  QGS / VGS(th) is more accurate for t2?

Edit4: I think that might have been correct; using QGS / VGS(th) to calculate tr and Ciss to calculate tf I get a rise time of 71 ns and a fall time of 33 ns, and plugging these into the DMC formula for power loss I get 0.037 W at 30 kHz and 0.012 W at 10 kHz. The power loss rises and falls with the value of the gate resistor by amounts that don't look totally wrong. I'll now try to double check this with additional simulation runs.

Edit5: Raising the gate resistor to 200 Ω (RG(tot) = 226 Ω) I get a 10 kHz switching loss of 0.019 W from the simulation, while the formula suggests 0.022 W. At 30 kHz the simulation gives 0.049 W, and the formula 0.067 W. Hmmm.
« Last Edit: June 14, 2024, 11:58:58 am by Lomax »

#### T3sl4co1l

• Super Contributor
• Posts: 22012
• Country:
• Expert, Analog Electronics, PCB Layout, EMC
##### Re: Estimating time spent on Miller Plateau (maths)
« Reply #31 on: June 14, 2024, 12:14:42 pm »
Ciss is a small-signal parameter, and not relevant here.  It varies: it's a function of operating conditions (and, notice the condition it's measured at in the table).  At best, you would integrate its value over the switching edge ($Q_G = \int C_\text{iss} dV$), which has the convenient byproduct that Miller effect manifests and all that, but, now you're bringing in enough data (you need the C(Vds) and gm curves) that you're better off doing it in SPICE, and needless to say, a brief closed-form relation is not applicable.

Given the tabulated Qg's, and assuming you're running at the same overall V, I as the test condition, you can calculate td/tr/tf from that; but varying Vgs(on), Vds, even Id, requires more effort: extracting Q(Vds) from the C curves, adjusting for transfer function (different Id), etc.

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!

The following users thanked this post: Lomax

#### Picuino

• Super Contributor
• Posts: 1022
• Country:
##### Re: Estimating time spent on Miller Plateau (maths)
« Reply #32 on: June 14, 2024, 02:09:51 pm »
The time spent on miller plateau is only a part of the total switching time when inductive loads are present.
First the voltage switches at the drain between GND and Vdd (miller plateau). Then the drain current decreases until it becomes zero.
The two times are important for calculating the heating of the mosfet by switching.

In the first case the power dissipated by the mosfet will be:
P = 2 * fc * T1 * Idd * Vdd * 0.5

In the second case the power dissipated by the mosfet will be:
P = 2 * fc * T2 * Idd * Vdd * 0.5

With:
fc = Switching frequency [Hz].
T1 = Time of miller plateau [ s]
T2 = Time of complete switch off or switch on (decrease or increase current to Idd) [ s]
Idd = Drain current = Inductor current [A]
Vdd = Supply voltage. [V]
2 = 2 transitions per cycle. On and Off
0.5 = Triangle area formulae

Therefore the switching time must also take into account the time during which the current is reduced to zero or increased to the inductor current (for both on and off switching).
« Last Edit: June 14, 2024, 02:11:58 pm by Picuino »

#### T3sl4co1l

• Super Contributor
• Posts: 22012
• Country:
• Expert, Analog Electronics, PCB Layout, EMC
##### Re: Estimating time spent on Miller Plateau (maths)
« Reply #33 on: June 14, 2024, 03:19:49 pm »
BTW, note that this is energy, but not actually power.  It's power dissipated, when it's current flowing through the channel.  You can also have the channel just turn off fast enough, and drain voltage rises on its own.  It's energy, but it's not power, it's energy stored in Coss and not yet dissipated.

This is the trick of ZVS, switch fast enough, and have something magically return Vds to ~0 before the next cycle, and that's it, you've won, efficiency is yours.

Which is why gate drive networks often have a speed-up diode, so that turn-off can be fast, and the drain swing is capacitive mediated, and incidentally this also violates Miller's theorem so there's no plateau (but the same charge still must be put into Cdg, it just flows while Vgs = Vgs(off), so it further pays to have a low-impedance driver in the low state).

A hard-switched converter, will absorb all that energy (and more) at turn-on, because, say for a buck/boost in CCM, turn-on has to drop the full supply/output voltage, plus commutate the diode (deliver all the recovery/junction charge it has), plus dissipate its stored Coss energy, and that basically makes up for all of it and more.  Whereas specifically for a slow-switched resistive load, the switching loss is ~equal (rising/falling), or more specifically proportional to time taken on each edge, and for a resistive load and linear ramp waveforms (constant device capacitances) you get V*I*t/3 rather than /2 because the power pulse is a quadratic spike rather than a triangular one.

Because Coss or Cj is dependent, and large at low voltage, the diode capacitance (or recovery, which can be modeled a similar way) in CCM at turn-on is a HUGE factor in overall switching loss.  It's got that full supply/output voltage in series with it to the switch, so the switch has to pull down from that voltage towards GND before current starts flowing, then ramps up, then finally voltage ramps down.  So you get the double-triangular inductive switching waveform, with an excess current peak due to Cj or recovery, and then the voltage ramp.

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!

#### iMo

• Super Contributor
• Posts: 4897
• Country:
##### Re: Estimating time spent on Miller Plateau (maths)
« Reply #34 on: June 14, 2024, 04:35:09 pm »
FYI - In the LTspice you may get the power plot with integrated numbers over a time period. For example below the power plot of the IRLL024Z during the 300us..
ALT+click on the transistor - you will get the power plot of the transistor in the graph, CTRL+click on the formula in the graph you will get averaged/integrated numbers over the simulation duration.

The following users thanked this post: Lomax

#### Picuino

• Super Contributor
• Posts: 1022
• Country:
##### Re: Estimating time spent on Miller Plateau (maths)
« Reply #35 on: June 14, 2024, 06:24:19 pm »
It is power dissipated in the transistor by joule effect during switching.
Because the current continues to flow through the transistor while the voltage is changing from Vdd to GND. Current times voltage is power.

The formula has units of voltage x current x time x frequency.
Time and frequency cancel each other to give a dimensionless number that represents the percentage of the time the transistor is in transition switching.
The voltage across the transistor times the current in the transistor gives units of power [watts].

To this power should be added the power dissipated during the driving phase:
P = D * Rdson * Idd ^ 2
« Last Edit: June 14, 2024, 06:26:43 pm by Picuino »

The following users thanked this post: Lomax

#### T3sl4co1l

• Super Contributor
• Posts: 22012
• Country:
• Expert, Analog Electronics, PCB Layout, EMC
##### Re: Estimating time spent on Miller Plateau (maths)
« Reply #36 on: June 14, 2024, 06:37:02 pm »
It is power dissipated in the transistor by joule effect during switching.
Because the current continues to flow through the transistor while the voltage is changing from Vdd to GND. Current times voltage is power.

Are you sure of this?

Consider the circuit:

Does Q3 dissipate power?

If so, how much?

(In fact this is a trick question, as the answer turns out to be "yes"; but "how much", requires knowing more about the specified part than the datasheet provides..!)

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!

#### Lomax

• Frequent Contributor
• Posts: 582
• Country:
• Minimalist
##### Re: Estimating time spent on Miller Plateau (maths)
« Reply #37 on: June 15, 2024, 07:37:47 am »
FYI - In the LTspice you may get the power plot with integrated numbers over a time period. For example below the power plot of the IRLL024Z during the 300us..
ALT+click on the transistor - you will get the power plot of the transistor in the graph, CTRL+click on the formula in the graph you will get averaged/integrated numbers over the simulation duration.

That's very convenient, thank you! I found the same functions in KiCAD's simulator by right-clicking the parameter in the parameter list on the right:

Here the average for t0 to the end of t3 (i.e. the switch-on period) is shown as 2.435763 W over 133 ns (at 10 kHz with 10% duty).

And above is the (slightly faster) switch-off period from start of t4 to end of t6, showing an average of 1.875544 W over 109 ns (at 10 kHz with 10% duty).
« Last Edit: June 15, 2024, 08:51:33 am by Lomax »

Smf