I'm trying to implement a counter circuit and the up/down counting logic isn't working properly. I was hoping to get some advice on a solution based on my analysis below. My objective is simple: turn the knob one way and the digits count upward, turn it the other way and they count downward. For some reason, I'm seeing double counts when the most significant digit changes.
This is a fairly straightforward two-digit decimal counter using a pair of cascaded 74HC191s and a rotary encoder. The binary counter output goes to some 74HC4511 BCD driver chips and 7-segment displays.

I'm using an
interface circuit from Bourns to decode the quadrature output from the encoder to produce clock and direction signals that the '191 can understand:

When I rotate the encoder to increase the count, the digits behave like this: 21, 22, ..., 29, 30, 40, 41, 42, ...and so on. There's an extra count on the ripple carry output from the least significant digit when the counter rolls over.
I was able to capture this behavior on my logic analyzer. For the sake of testing, I'm outputting a square wave (Ch0) from my function generator and doing a 90-degree phase shift with some flip-flops to produce a quadrature signal (Ch1/Ch2) akin to the rotary encoder. This eliminates the mechanical hardware and makes it easier to consistently capture the data. Ch3 and Ch4 are the outputs from the Bourns interface circuit. As you can see on Ch5, the RCO output has an extra transition that is causing the erroneous counting.

Now, if I hardwire the U/D signal either high or low, the counting behaves as expected. In the capture below, U/D is held low and RCO only sees one transition. The CLK signal is still coming from the Bourns circuit.

If we zoom in on the "bad" behavior, it's evident that the RCO is triggering on the falling edge of the U/D signal produced by the Bourns circuit. The extra count "inside" is a result of the CLK transition (or possibly the U/D rising edge). Compared to the "good" behavior, the RCO triggers between CLK pulses as expected.


Keep in mind that none of the above examples are actually changing the direction of the count. Due to the nature of the Bourns circuit, the U/D signal will always transition in accordance with the quadrature signal, so it'll never be pulled high or low for more than one clock cycle. I'm
thinking that the issue here might have something to do with the 74HC191 itself. The
datasheet explicitly states that U/D should only be changed when the clock signal is high. Unfortunately, the Bourns circuit doesn't do this, even though it sufficiently pulls U/D one way or another before the clock transitions.

That all being said, I'm left with the following questions:
- Am I sufficiently understanding the problem here, or am I missing something?
- What quadrature decoder circuits do work with the '191?
- Is the Bourns circuit intended for some other application or chip? (The 4029 counter, for instance, makes no mention of restrictions on U/D transitions. I don't have one of those chips on hand to test, unfortunately.)
- Any other options or advice? I'm looking for a discrete (non-MCU) counting solution.
Thanks for reading this far. I've searched high and low for answers, but I haven't had any luck. I'm looking forward to hearing some ideas.
