Author Topic: Course/fine DAC aka Fake resolution DAC design.  (Read 10605 times)

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Offline (In)Sanity

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Course/fine DAC aka Fake resolution DAC design.
« on: January 14, 2013, 02:32:51 am »
So I'm converting my home brew PSU design to a micro driven design and I'm trying to be a cheap bastard (as always).   I was wondering if anyone has had any experience with using two DAC in a voltage divider setup to obtain a fine and course resolution?   

Something like what is mentioned in Fig 21 of this sheet.

http://www.analog.com/static/imported-files/application_notes/49951363AN142.pdf

My goal is to obtain the most resolution I can for the lowest cost and still have a stable design.   I'm going to use a 16 bit ADC to read the output voltage and display it on a 20x2 LCD for both voltage and current.   The entire analog part of the design has been done for about a year now and handles 3mv to 30 volts and 3ma to 5 amps.   The 3mv/ma is due to a crappy op-amp I'm using.   That's going to be replaced with a far far better chip.    The control signals to this analog design accept 0-5 volts for their set point.   So I designed it to be driven from a DAC or a POT from the start.   The voltage reference is a higher grade TL431BC which has proven to be very stable.   I can leave it with an analog pot controlling it at 5.000 volts for days and it won't drift up or down.   The current limiting also has proven very stable.   

Ok,  I strayed off topic.    So any pointers on using a course/fine DAC setup ?  I'm aware the accuracy will suffer greatly,  I really just want resolution.   The 16 bit ADC reading the values will tell me what I'm set to.   So linear is not as big of a concern.    I would love to get 20 bits or better resolution.  Stupid 3457A has made me a digit junkie.

Thanks,

Jeff

 

Offline UPI

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Re: Course/fine DAC aka Fake resolution DAC design.
« Reply #1 on: January 14, 2013, 03:14:29 am »
This may not be right for what you are after, but I was considering adding an analog pot to adjust the VREF of a 10 bit DAC to allow for a fine adjustment.

« Last Edit: January 14, 2013, 03:16:26 am by UPI »
 

Offline (In)Sanity

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Re: Course/fine DAC aka Fake resolution DAC design.
« Reply #2 on: January 14, 2013, 03:44:47 am »
This may not be right for what you are after, but I was considering adding an analog pot to adjust the VREF of a 10 bit DAC to allow for a fine adjustment.

Thanks,  hopefully someone has experience with this type of circuit design.  From what I can gather I would need to trim the ratio in such a way that the fine DAC at it's highest value is exactly one of it's steps in voltage below the first step in the course DAC.   

So taking two 8 bit DAC's for example with a 5 volt reference the 255 value on the fine adjust DAC would produce 19.5mv which would be added to the value from the course adjust DAC which would step 19.5mv on a value of 1.   The exact numbers of course would be slightly different.   The idea being to in a sense extend the two DAC's together to make a larger R2R ladder circuit.   The fine tuning on the divider however might be a bit touchy to say the least.  Again hopefully someone has done this and has some pointers.   Perfection isn't needed,  but hopefully I can get it close.

Jeff
 

Offline Mr Smiley

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Re: Course/fine DAC aka Fake resolution DAC design.
« Reply #3 on: January 14, 2013, 03:56:08 am »
Put the outputs of the two DA's into a single opamp adder.  :-//

 :)
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Offline free_electron

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Re: Course/fine DAC aka Fake resolution DAC design.
« Reply #4 on: January 14, 2013, 04:09:58 am »
screw the dac. use three programmable pots ...

two pots are connected between VREF and GND.  the wipers go to the extents of the third pot ...
you simply program one pot to be always one step higher than the other...

Code: [Select]
vref ----+---------------+
         |     out       |
         /      |        /
         \      v        \
      P1 /<--/\/\/\/---->/ P2
         \     p3        \
         /               /
         |               |
gnd------+---------------+

program P1 to be always 1 step higher than P2.  P3 is then fine tunable between those steps ...
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Offline (In)Sanity

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Re: Course/fine DAC aka Fake resolution DAC design.
« Reply #5 on: January 14, 2013, 04:47:12 am »
screw the dac. use three programmable pots ...

two pots are connected between VREF and GND.  the wipers go to the extents of the third pot ...
you simply program one pot to be always one step higher than the other...

Code: [Select]
vref ----+---------------+
         |     out       |
         /      |        /
         \      v        \
      P1 /<--/\/\/\/---->/ P2
         \     p3        \
         /               /
         |               |
gnd------+---------------+

program P1 to be always 1 step higher than P2.  P3 is then fine tunable between those steps ...

Thanks,

It's been a long day,  what's the net resolution end up being?   Also the analog portion of my circuit is already designed,  testing and working with 0-5 volt inputs.   Would the 3 programmable pots offer an advantage over the DAC design when I'm already setup for voltage control ?  I could see an advantage if you were using current control,  etc.

Jeff

Edit:   If I'm not mistaken that actually works out to be 24 bits of resolution with 8 bit pots.   Hmm.  This might be cost effective. 
« Last Edit: January 14, 2013, 05:45:17 am by (In)Sanity »
 

Offline Harvs

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Re: Course/fine DAC aka Fake resolution DAC design.
« Reply #6 on: January 14, 2013, 05:19:22 am »
Put the outputs of the two DA's into a single opamp adder.  :-//

 :)

This is what I've done before, using two 8-bit pwms on the uC, filtered and summed to produce about 13-14 bits of resolution.  There's a LT app note on using two 16-bit DACs summed, then a LT2400 ADC as feedback to generate a 1ppm voltage source.  It's a good read, one of the Jim Williams ones.
 

Offline (In)Sanity

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Re: Course/fine DAC aka Fake resolution DAC design.
« Reply #7 on: January 14, 2013, 05:30:50 am »
Put the outputs of the two DA's into a single opamp adder.  :-//

 :)

This is what I've done before, using two 8-bit pwms on the uC, filtered and summed to produce about 13-14 bits of resolution.  There's a LT app note on using two 16-bit DACs summed, then a LT2400 ADC as feedback to generate a 1ppm voltage source.  It's a good read, one of the Jim Williams ones.

I absolutely love this idea..except for one problem.   I'm a cheap bastard :)  The 24 bit ADC (LTC2400) is over $10.  Toss in the two 16 bit DAC's and you might as well just buy a power supply.   

On another note,  I am going to use a 16 bit ADC for the voltage and current readouts.   So in theory I could have the micro scan up and down the voltage range using the summed non perfect DAC's until it found a number it likes.   Kind of the same concept but without extra cost.   

Here is another thought,  combine two techniques together.   Using a rotary encoder you select the voltage you want,  the micro adjusts the DACs to the approximate setting and uses the ADC to narrow it in.  If I used 12 bit summed DAC's I might be able to get close to 24 bit resolution.  Now clicking the rotary encoder could allow for 24 bit fine tuning.   So the micro could do 16 bit voltage set with the option to fine tune to 24 bit.   Noise and such would of course make this more like 20 bits..but you get the idea.

Jeff
 

Offline free_electron

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Re: Course/fine DAC aka Fake resolution DAC design.
« Reply #8 on: January 14, 2013, 06:02:33 am »
adding two 12 bit dacs does not give you 24 bits ...

besides why do you need so many bits ? shall we take a look at the absurdity ?
10 bit is 1024 steps so 12 bits 4096 steps. Assuming you make a supply that does 0 to 20 volts this gives you 5 millivolt per step. You'll have to have a killer regulation system to get the output noise of the supply be below 10mV peak/peak under all load and line conditions... so your step size is already below the noise band. useless...
Even if you were to do a weighted system using two dacs /.. how do you handle the non-monotonicity  of the DAC (INL/DNL). any attempt to 'jiggle' between steps will create random behavior. So this approach fails as well.

You use an Lt431 as reference ? that's not a reference .... if you want any kind of precision from your adc or dac start looking at real reference chips.

As for the ADC. get a microcontroller like an ADuC8xx series or a Silabs 900 series. Those come with 24 bit ADC's on board... and matching references. These micros are relatively cheap and have differential input stages so you can sense where it matters.

Now, here is the same problem as with the DAC : the noise band of the PSU ...

There are extreme power supplies around. Rohde&Schwarz NGPS comes to mind... that is a power supply that can make -32 to +32 volts in steps of 500 microvolts and that sucker is spot on... maximum current is 100 milliampere. You do NOT want to know what it costs ...

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Offline (In)Sanity

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Re: Course/fine DAC aka Fake resolution DAC design.
« Reply #9 on: January 14, 2013, 07:50:54 am »
adding two 12 bit dacs does not give you 24 bits ...

Adding DAC + DAC, no.  Using a voltage divider yes.   The fine DAC does the same range as one step on the course DAC.  You end up with for example 256 steps per each of the 256 steps resulting in 65536 or 16 bits from two 8 bit DAC's.   Alignment appears to be a bitch however.

besides why do you need so many bits ? shall we take a look at the absurdity ?
10 bit is 1024 steps so 12 bits 4096 steps. Assuming you make a supply that does 0 to 20 volts this gives you 5 millivolt per step. You'll have to have a killer regulation system to get the output noise of the supply be below 10mV peak/peak under all load and line conditions... so your step size is already below the noise band. useless...
Even if you were to do a weighted system using two dacs /.. how do you handle the non-monotonicity  of the DAC (INL/DNL). any attempt to 'jiggle' between steps will create random behavior. So this approach fails as well.

Mostly because it's interesting to be able to do so.   The analog portion has proven very clean and stable.  Linear of course which sits around 1mv with a light load.   For the jitter you have to use a latched synchronous update DAC or in this case two DAC's in one chip.   The voltages present themselves to the divider at the same time.   Well close enough not to matter.   I agree if you updated one DAC and then the other you'll have lots of jitter.   

You use an Lt431 as reference ? that's not a reference .... if you want any kind of precision from your adc or dac start looking at real reference chips.

Without a doubt,  amazingly I've been able to get a few of these shunt regulators to maintain the last digit on my 3457 for hours on end.   98% of them however don't.   Long term,  no they are complete junk.   

As for the ADC. get a microcontroller like an ADuC8xx series or a Silabs 900 series. Those come with 24 bit ADC's on board... and matching references. These micros are relatively cheap and have differential input stages so you can sense where it matters.
 

I've been working with PIC's for too long to change up now.   External components will need to do.   Keep in mind also that this is an exercise in being cheap,  not one of precision.   It's getting more then you normally would out of little or no extra money.   

Now, here is the same problem as with the DAC : the noise band of the PSU ...

Agreed,  any extra resolution will just end up adding to the noise band offsetting the net average.  It's all linear,  so at least it has a fighting chance.   In the end it's all gravy and interesting none the less.   Now picture the same supply slowing charging a large cap through a resistor,  would the extra 1uV of voltage show up ?  Hmm.   

Jeff
 

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Re: Course/fine DAC aka Fake resolution DAC design.
« Reply #10 on: January 14, 2013, 09:03:05 am »
screw the dac. use three programmable pots ...

two pots are connected between VREF and GND.  the wipers go to the extents of the third pot ...
you simply program one pot to be always one step higher than the other...

Code: [Select]
vref ----+---------------+
         |     out       |
         /      |        /
         \      v        \
      P1 /<--/\/\/\/---->/ P2
         \     p3        \
         /               /
         |               |
gnd------+---------------+

program P1 to be always 1 step higher than P2.  P3 is then fine tunable between those steps ...
You still have the same problem when using 2 DACs! Besides a 12 or 14bit DAC isn't that expensive.
There are small lies, big lies and then there is what is on the screen of your oscilloscope.
 

Offline Harvs

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Re: Course/fine DAC aka Fake resolution DAC design.
« Reply #11 on: January 14, 2013, 11:28:14 am »
(In)Sanity - I'm not suggesting you build what's in that app note, it would clearly be of no use in a power supply, just a waste of money.

However, the details of some of the topics that free_electron has touch on are explained in detail. 

I'm just suggest you have a good read through it prior to embarking down this path, could save you some disappointment of matching expectation to reality.

Quote
Adding DAC + DAC, no.  Using a voltage divider yes.   The fine DAC does the same range as one step on the course DAC.  You end up with for example 256 steps per each of the 256 steps resulting in 65536 or 16 bits from two 8 bit DAC's.   Alignment appears to be a bitch however.

Nope. Yes if you simulate it in SPICE.  But in reality the non-idealities of the DAC will prevent this.  That's why that app note uses two 16-bit DACs and one of the best 24bit ADCs available to realize about 20-bits of true resolution.
 

Offline CarlG

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Re: Course/fine DAC aka Fake resolution DAC design.
« Reply #12 on: January 14, 2013, 11:53:15 am »
I haven't used the solution you're referring to (Fig 21). Another option is to tie the output from one DAC to the reference of a multiplying DAC. I think I've seen an ADI application note about it some time.

It should work with a digital pot instead of the MDAC as well. Using an "ordinary" DAC for the second may also work, but the performance might be affected, depending on the min Vref for it.

//C
 

Offline hlavac

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Re: Course/fine DAC aka Fake resolution DAC design.
« Reply #13 on: January 14, 2013, 12:37:38 pm »
Real cheap bastards use R-2R ladders, driven from 74hc164 powered from 5V reference :)

But for the 16 bits you will have problem finding precise enough resistors (0.0015%).
R-2R stops being practical beyond 8 bits and 0.1% resistors...

You could try trimming, but it would not be easy, you would need very high precision ohm meter, or a special calibration circuit...
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Offline (In)Sanity

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Re: Course/fine DAC aka Fake resolution DAC design.
« Reply #14 on: January 14, 2013, 01:50:31 pm »
Without a doubt I hear what everyone is saying.   You don't get something for nothing.   But the question really is..do you get something at all?    Does 1+ 1/100th of 1 equal something greater than 1 ?    If it does then that's all I need.    The idea is not to get precise steps but to get additions to or increases in the target voltage.   

So for example if the micro used the course 12 bit DAC for all of it's work and the fine DAC was just used for adjusting in between the course DAC's steps it still obtains something.   For a 30 volt range with a 12 bit DAC you end up with just over 7.3 mv per step.  With the fine DAC back in play one could easily get half way in between that step,  quarter way between that step, etc.    True 24 bit resolution,  no.   What you might get is 20 bit resolution that sometimes increases a bit or two under certain circumstances.   Accuracy,  hell no.   Don't need it.   I've actually opted to go with an 18 bit ADC to get my voltage and current readings.   So I see no reason at all why the two 12 bit DAC's can get the voltage where that 18 bit ADC wants it to be.   Does 1 + something not equal more then 1 ?   Perhaps a 12 bit DAC paired with an 8 bit.   
Jeff
 

Online nctnico

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Re: Course/fine DAC aka Fake resolution DAC design.
« Reply #15 on: January 14, 2013, 02:25:34 pm »
The problem is that DACs and ADC are not accurate down to their last bits. If you set the DAC in your example to output 10V it may actually be off by +/-36mV if you use a DAC with a 5LSB accuracy. You could use fine/course DACs but you'll need a way to measure the error and compensate for that. In other words: you'll need a circuit with an ADC to measure the actual DAC values. Fortunately slow but high resolution ADCs are not extremely expensive.
There are small lies, big lies and then there is what is on the screen of your oscilloscope.
 

Offline CarlG

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Re: Course/fine DAC aka Fake resolution DAC design.
« Reply #16 on: January 14, 2013, 02:33:41 pm »
Without a doubt I hear what everyone is saying.     
Hi Jeff,
Except for me then, I assume? Or was my message misinterpreted? E.g. AD5312 might do the job, has a multiplying bandwidth of 200 kHz.

//C
 

Offline CarlG

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Re: Course/fine DAC aka Fake resolution DAC design.
« Reply #17 on: January 14, 2013, 02:41:31 pm »
The problem is that DACs and ADC are not accurate down to their last bits. If you set the DAC in your example to output 10V it may actually be off by +/-36mV if you use a DAC with a 5LSB accuracy. You could use fine/course DACs but you'll need a way to measure the error and compensate for that. In other words: you'll need a circuit with an ADC to measure the actual DAC values. Fortunately slow but high resolution ADCs are not extremely expensive.

If the DAC is monotonic you'd still get resolution, which is what Jeff wants. And if I get it right, he wants to use the 16 bit ADC to read the actual output voltage. That will need some averaging and interpolation, and obviously hard to verify to the last bit, but heck, he's just doing for the fun of it?

//C
 

Online ve7xen

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Re: Course/fine DAC aka Fake resolution DAC design.
« Reply #18 on: January 14, 2013, 03:40:43 pm »
There are apparently some errors in the schematics but I believe the concept is sound. Anyone seen this approach?

http://www.edn.com/design/other/4326640/DC-accurate-32-bit-DAC-achieves-32-bit-resolution
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Offline (In)Sanity

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Re: Course/fine DAC aka Fake resolution DAC design.
« Reply #19 on: January 14, 2013, 04:06:39 pm »
I haven't used the solution you're referring to (Fig 21). Another option is to tie the output from one DAC to the reference of a multiplying DAC. I think I've seen an ADI application note about it some time.

It should work with a digital pot instead of the MDAC as well. Using an "ordinary" DAC for the second may also work, but the performance might be affected, depending on the min Vref for it.

//C

My apologizes Carl,  I didn't overlook your post,  it just didn't register correctly in my head.   Your idea is actually a very good one.   Well worth looking in to further.   I suspect it would be more accurate and stable then just using a resistive divider. 

Jeff
 

Offline free_electron

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Re: Course/fine DAC aka Fake resolution DAC design.
« Reply #20 on: January 14, 2013, 04:26:05 pm »
Ah, so we are going the el cheapo tour... Well ,simply build your own adc based on the dual slope principle. All you need is an opamp and a comparator and two analog switches. You can use the counters in the pic to do the runup and rundown. That's what all the high end meters do. Even you 3457
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Offline (In)Sanity

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Re: Course/fine DAC aka Fake resolution DAC design.
« Reply #21 on: January 14, 2013, 05:42:38 pm »
Ah, so we are going the el cheapo tour... Well ,simply build your own adc based on the dual slope principle. All you need is an opamp and a comparator and two analog switches. You can use the counters in the pic to do the runup and rundown. That's what all the high end meters do. Even you 3457

Too funny,   yes I've already looked at this option and may take it in to consideration.   The dual slope converter can work really well..as you pointed out.   Speed is not even that big of an issue for my needs.   Cheap can be a learning experience which is what I often enjoy most.

Jeff
 

Offline jerry507

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Re: Course/fine DAC aka Fake resolution DAC design.
« Reply #22 on: January 14, 2013, 05:52:16 pm »
So as I read these two pages, I'm not entirely clear what you want. It seems like you want to build a very accurate output voltage set circuit, that is you want to punch in 512 out of 1024, have that turn into 2.5V and have 2.5V turn into 10V on a 20V PSU. Without having to do any feedback or trimming.

Yet this fine/course thing you're using would seem to lend itself far easier to just trimming once you're measuring from a high precision and very accurate voltmeter.

If you want to be accurate out of the box, you'll need high resolution, good stability and either very accurate parts or good calibration. You can't have your cake and eat it too, so expect it to be expensive.

If you're fine trimming it by looking at your nice meter, then you can get away with high resolution, maybe add in good stability if you want that feature. But you need to more clearly define what you want to do, because you have to cut some cost out somewhere.
 

Offline Jay_Diddy_B

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Re: Course/fine DAC aka Fake resolution DAC design.
« Reply #23 on: January 14, 2013, 06:15:02 pm »
Hi,

I would sugest reading Linear Technology Application note AN86.

http://cds.linear.com/docs/Application%20Note/an86f.pdf

Jay_Diddy_B

 

Offline Bored@Work

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Re: Course/fine DAC aka Fake resolution DAC design.
« Reply #24 on: January 14, 2013, 06:59:45 pm »
OK, so you just want to have a warm feeling when turning a knob or sending a commad that you can select 20^2 or even more values? Independent if this makes sense and of accuracy and precision?

So here we go. What about doing 2^32 values? Not that it makes sense, but ... Look for 16 bit hardware pwm in your micro controller. Add an RC filter and a buffer to the pwm output. Until now this is all prety standard and gives you a simple, imprecise DAC (the MCU's Vcc being the voltage reference is one of the problems).

Now the fun starts. Use a 32 bit word to set the desired value. Round it to the 16 MSBs. Calculate the difference between the original value and the rounded value. This is your start error value. Take the rounded 16 MSBs, shift them 16 times to the right and load the result into the pwm duty cycle register.

Run a hardware timer in addition to the pwm, at the pwm frequency or a multiple of that frequency. Let the timer change the pwm duty cycle value by one bit, on averrage for error/16^2 timer periods.

You now have probably the world's cheapest, useless, crappy 32 bit DAC.

One way to improve that DAC is to just throw away the error and not have that timer.



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