Author Topic: Course/fine DAC aka Fake resolution DAC design.  (Read 10612 times)

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Offline A Hellene

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Re: Course/fine DAC aka Fake resolution DAC design.
« Reply #25 on: January 14, 2013, 09:22:47 pm »
Accuracy is a bitch; a really expensive one, especially when high resolution is a requirement!

This is the problem with the "affordable" (== el-cheapo) DACs, put in ruthless numbers.
On the other hand, this is an ultra-high resolution approach using an ordinary 8-bit AVR running a delta-sigma DAC algorithm! The PWM approach is probably the best way around the DAC monotonicity problem.


-George
Hi! This is George; and I am three and a half years old!
(This was one of my latest realisations, now in my early fifties!...)
 

Offline (In)Sanity

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Re: Course/fine DAC aka Fake resolution DAC design.
« Reply #26 on: January 14, 2013, 11:50:44 pm »
Accuracy is a bitch; a really expensive one, especially when high resolution is a requirement!

This is the problem with the "affordable" (== el-cheapo) DACs, put in ruthless numbers.
On the other hand, this is an ultra-high resolution approach using an ordinary 8-bit AVR running a delta-sigma DAC algorithm! The PWM approach is probably the best way around the DAC monotonicity problem.


-George

Lots of good feedback on this so far.  Some positive and some more or less saying...your off your rocker.   But hey it's all about learning and trying new things...right?   

The PWM approach might be a good one.  I'll have to do some research on IC's out there.   Microchip has some dual output synchronous latched 12 bit DAC's that might be helpful as well.   The multiplying approach I think perhaps has the most promise.   In the end I may end up just saying screw it and order some 16 bit DAC's.   I think I owe it to myself to at least try some other designs.   Keeping in mind again it's not the accuracy I want..but the resolution.   If I want accuracy I'll connect up my 3457A and adjust the output.    Of course without the resolution it might be a bit frustrating.   

Jeff
 

Offline CarlG

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Re: Course/fine DAC aka Fake resolution DAC design.
« Reply #27 on: January 15, 2013, 07:29:59 am »
I haven't used the solution you're referring to (Fig 21). Another option is to tie the output from one DAC to the reference of a multiplying DAC. I think I've seen an ADI application note about it some time.

It should work with a digital pot instead of the MDAC as well. Using an "ordinary" DAC for the second may also work, but the performance might be affected, depending on the min Vref for it.

//C
It took me a good night's sleep to realize what probably all of you immediately realized :-[ That my proprosal won't give a true M+N bit DAC. It will give overlapping "ranges", i.e. the scale set by the first DAC will always range from Vref- (typically zero)  to Vref+ of the 2nd. It gives good resolution at low levels, but still only N bits at max range.

//C

 

Offline (In)Sanity

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Re: Course/fine DAC aka Fake resolution DAC design.
« Reply #28 on: January 15, 2013, 03:47:29 pm »
I haven't used the solution you're referring to (Fig 21). Another option is to tie the output from one DAC to the reference of a multiplying DAC. I think I've seen an ADI application note about it some time.

It should work with a digital pot instead of the MDAC as well. Using an "ordinary" DAC for the second may also work, but the performance might be affected, depending on the min Vref for it.

//C
It took me a good night's sleep to realize what probably all of you immediately realized :-[ That my proprosal won't give a true M+N bit DAC. It will give overlapping "ranges", i.e. the scale set by the first DAC will always range from Vref- (typically zero)  to Vref+ of the 2nd. It gives good resolution at low levels, but still only N bits at max range.

//C

Yes,  correct.   The resistor divider approach would be a bit better in this regard.  It however produces a non linear curve as well.   A more proper summing amp might help out.   But then we get in to a whole new area of introducing potential noise to an already challenged design.     What I need to do is get some parts on order and start doing some testing.   I may run some spice models as well just to get a rough idea what to expect.  Reality of course won't be the same.  I'm mostly interested in how the two DAC's will interact.  How low can the impedance of the divider go before it starts to cause issues with the output impedance of the two DAC's,  voltage drops in areas you don't want,  etc.   All I have on hand at the moment for DAC's are high speed "flash" types.    I think I might have a couple 6 bit CDIP flash chips floating around.   Those would work for testing.   I really need to get a GPIB interface for my 3457A.

Jeff
 


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