How to build a simple tri-level sync generator for 1080p60?

[Yansi]

Hello,

I am currently facing a kind-of an issue, that a piece of equipment I have requires an external genlock to work reliably. I do not own any such instrumentation I could use directly, so I thought I could likely cobble something together for the test.

From my brief investigation,  standard definition television uses just plain old composite video (sync+black + colorburst).

High definition television uses a tri-level sync. I have found how the pulse is shaped (-+300mV pulse for 40 sample clocks), however I did not find much useful info how the whole frame looks and what pulsetrains it contains.

This PDF is so far the most helpful: http://www.tek.com/dl/20W_18580_0_0.pdf although it does not seem to be extensive enough to implement a makeshift sync generator based on this.

What would be the easiest way to build a genlock source for 1920x1080 60Hz progressive scan resolution? I guess a microcontroller with a bunch of resistor D/A could be enough to generate the whole mess with the help of a couple of HW timers.

..or at least so do I think.
Thanks for suggestions,
Y.

[flynwill]

HD timing might be a bit fast to be able to do well with a small micro.  It would be an interesting project for a small FPGA.

However far simipler would be to look for a used generator on EBay.  There's a seller of use AJA GEN10 units for $70 at the moment.

[Yansi]

Buying another used equipment is not the thing I would currently want, although having a proper 19" rack mount instrument as a fully configurable genlock source would be handy, I am not against further improving my knowledge and skills.

Why do you think it is too fast for an MCU?  Line rate is about 67kHz, which is well within what I can easily generate using a bunch of linked HW timers. I am not talking a stupid arduino here. Heck I could even almost generate 720p60 (720p30 for sure) image directly with a suitable ARM MCU.

FPGA would of course be better suited for this task, but I still think this could be cobbled up using a suitable MCU dev board (toy duino is not one of those I've thought of).

I would almost buy the AJA GEN10, unfortunately, it can't do 1080p60 - so no use for me.

[flynwill]

Ah, sorry I thought the aja unit could to 60p, but I see that it can't.

The doc you linked has all the details you need.  You can see that the individual bits of the tri-level H-sync pulse for 1080p60 are 298 nS each.  If your MCU can indeed do that (and perhaps it can with careful choice of the primary clock frequency), I'd say go for it.
 
I'm curious what is the gear that needs tri-level sync to operate?

[Yansi]

Well I got a used tvONE C2-8210 video switcher, which was sold as a quote: "perfect working order". Unfortunately, I have found, that when the unit is not genlocked or reference-locked to any video inputs, it produces glitches in the video output - I guess due to out of spec internal clock source. Might have drifted away badly? Or jitter beyond acceptable? I do not know. What I know, is that the video output is useless when not genlocked. Many devices can't even handle the data from the unit at all.

The unit has three possible sources for reference: A dedicated genlock input and two DVI video inputs that can also be used for a reference video input. I have not tested the genlock input yet, so that is what I would like to do now.

Unfortunately, I also do not have any proper equipment I could for example analyze jitter on the output TMDS clock line in the DVI output (oscilloscope with a multiGHz sampling head or a proper spectrum analyzer is unfortunately out of my budget now and also likely in the near future).  But I could visit a friend of mine that could likely measure this.

I wanted to test whether the issue could be overcome also by using the genlock input, as forcing a fakin windows computer to output an exact timing and let alone the right resolution is almost mission impossible. And I would like to do without a computer in the first place.

So, that is why I want to try cobble up a genlock generator to test the above.

298ns shouldn't be the problem, nor would it be a problem to clock a timer at a multiple of the video pixel frequency, such as 27MHz (reference for a PLL).  Pixel clock is 148.5MHz for 1080p60 and it seems to me all pulse widths and positions should be even  possible to produce even at half the clock (74.25MHz).

//EDIT: I forgot to mention that I do not know if the crapped out video output (without a genlock) is a bug or a feature of the above mentioned unit. Other tvONE instrumentation I have seems to operate reliably even without a genlock. Hence I think this is either crapped HW or firmware bug. 

//EDIT2: (Well, to be honest, I think it is either a bug or HW fault, no way this behavior is normal). I am currently in touch with the tvONE support, but we have not reached far yet, but I guess I will have to try repairing the unit myself anyway.