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| CPU Clock Speed based on MOSFET Physics Gate Length, Electic Field... |
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| Agent:
Thanks for the help! Mathematically I couldn't find a good way to model clock speed based off just the physics. So instead I looked at the actual data from processors. Let's say clock speed is purely a function of gate length, electric field, and mobility. If I fix the electric field and mobility, then extending to 2004, my gate length is 60 times smaller. At 3000 um we got speeds of 10 MHz. So shorting the gate length would multiply the clock speed by 60 times. ( The data clearly doesn't show this. It's WAYYY better than that) If you look at the graph though, it's actually pretty close in the beginning. 1500 nm gate gives about twice the speed of 3000 nm. ( I guess the huge increase later on came from the switch to copper interconnects) So if everything scaled exactly with gate length at 50 nm we should have 600 MHz processors.(Which is a lot lower that actual processors at 50 nm) With this under estimate, it would then be fair to say that if the new material had 10x the mobility of silicon, it should be able to achieve 10x the speed, 6 GHz. |
| David Hess:
--- Quote from: T3sl4co1l on December 12, 2018, 05:59:33 pm ---Going back to the original topic a bit -- has there been any serious research (i.e., motivated by reduced power consumption, in fine-scale processes) regarding "lossless computation"? Namely, AC synchronous logic that draws mostly reactive power (junction capacitance). I wonder if the advantage is completely swamped by the dominant resistance in interconnects and such small transistors. --- End quote --- I know I have read papers on it in the past decade. The major problem appears to be the same as with asynchronous logic; there is a lack of simulation and development tools and the processes are only characterized for standard synchronous logic. |
| Miyuki:
BTW for example IBM Power CPUs are made for high clock for expense of extreme power consumption Even old Power 6 made on 65 nm was up to 5GHz (released at 2008) More modern Power 8 on 22 nm have also 5GHz version But power demand is extremely and are only used when need single core performance |
| Berni:
Yeah the transistor size doesn't really have that much to do with max clock speeds. For example take this CPU: https://ark.intel.com/products/27510/Intel-Pentium-4-Processor-supporting-HT-Technology-4-00-GHz-2M-Cache-1066-MHz-FSB Its a Pentium 4 from 2005 on a 90nm process running at 4GHz. Turn it forwards to today we for example get this: https://www.intel.com/content/www/us/en/products/processors/core/i9-processors/i9-9900k.html This is the worlds fastest x86 CPU for single threaded loads. It still runs on a base clock of 4GHz despite being a 14nm technology (Okay it does boost up to 5GHz but still). However it does so on 8 cores while having a TDP lower than the Pentium 4 up there. The transistor feature size is only one of the parameters that is getting optimized in new chip manufacturing processes. There are lots of other factors that get improved along the way but the transistor size is very important since given the example above going from 90nm to 14nm lets you put 6 times as many transistors on the same size of silicon. And this is where mostly the extra computing power was coming from in the last 10 years. More transistors doing more work per cycle at the same clock speeds. |
| David Hess:
--- Quote from: Berni on December 15, 2018, 01:00:41 pm ---https://www.intel.com/content/www/us/en/products/processors/core/i9-processors/i9-9900k.html This is the worlds fastest x86 CPU for single threaded loads. It still runs on a base clock of 4GHz despite being a 14nm technology (Okay it does boost up to 5GHz but still). However it does so on 8 cores while having a TDP lower than the Pentium 4 up there. --- End quote --- It is actually worse than that. Older Core2 processors had a load-to-use latency of 3. I forget exactly where but one of the changes was to add pipeline stages and logic to support a load-to-use latency of 4 so despite a greater load-to-use latency, the clock speed did not increase by a commensurate amount. The increase in load-to-use latency made up for decreasing cache performance. Was any of that from a decrease in transistor performance? This is why out-of-order execution is required for high clock speeds; it hides memory latency with a longer load-to-use latency. And predictive execution is required to fill the out-of-order execution pipeline with useful work. William Holt of Intel in 2016 discussing how Moore's Law applies even when transistor performance decreases. Moore's Law is about the price per transistor. |
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